qemu-e2k/target/riscv
Markus Armbruster 9c0928045c Clean up ill-advised or unusual header guards
Leading underscores are ill-advised because such identifiers are
reserved.  Trailing underscores are merely ugly.  Strip both.

Our header guards commonly end in _H.  Normalize the exceptions.

Macros should be ALL_CAPS.  Normalize the exception.

Done with scripts/clean-header-guards.pl.

include/hw/xen/interface/ and tools/virtiofsd/ left alone, because
these were imported from Xen and libfuse respectively.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20220506134911.2856099-3-armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-11 16:50:01 +02:00
..
insn_trans target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
cpu_bits.h target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
cpu_helper.c hw/intc: Make RISC-V ACLINT mtime MMIO register writable 2022-04-22 10:35:16 +10:00
cpu_user.h
cpu-param.h
cpu.c target/riscv: add scalar crypto related extenstion strings to isa_string 2022-04-29 10:47:46 +10:00
cpu.h target/riscv: rvk: add cfg properties for zbk* and zk* 2022-04-29 10:47:45 +10:00
crypto_helper.c target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
csr.c target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
debug.c target/riscv: csr: Hook debug CSR read/write 2022-04-22 10:35:16 +10:00
debug.h target/riscv: csr: Hook debug CSR read/write 2022-04-22 10:35:16 +10:00
fpu_helper.c target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
gdbstub.c target/riscv: correct "code should not be reached" for x-rv128 2022-02-16 12:24:18 +10:00
helper.h target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
insn16.decode target/riscv: accessors to registers upper part and 128-bit load/store 2022-01-08 15:46:10 +10:00
insn32.decode target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
instmap.h
internals.h target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_riscv.h target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm-stub.c target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm.c Remove qemu-common.h include from most units 2022-04-06 14:31:55 +02:00
m128_helper.c target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
machine.c target/riscv: machine: Add debug state description 2022-04-22 10:35:16 +10:00
meson.build target/riscv: rvk: add support for zknd/zkne extension in RV32 2022-04-29 10:47:45 +10:00
monitor.c target/riscv: Fix incorrect PTE merge in walk_pte 2022-04-29 10:47:46 +10:00
op_helper.c target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
pmp.c target/riscv/pmp: fix NAPOT range computation overflow 2022-04-22 10:35:16 +10:00
pmp.h target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
sbi_ecall_interface.h Clean up ill-advised or unusual header guards 2022-05-11 16:50:01 +02:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h
translate.c target/riscv: rvk: add support for zknd/zkne extension in RV32 2022-04-29 10:47:45 +10:00
vector_helper.c target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 2022-04-22 10:35:16 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00