a09410ed1f
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448) The QEMU-side software TLB implementation for the 7450 family of CPUs is being removed due to lack of known users in the real world. The last users in the code were removed by the two previous commits. A brief history: The feature was added in QEMU by commit7dbe11acd8("Handle all MMU models in switches...") with the mention that Linux was not able to handle the TLB miss interrupts and the MMU model would be kept disabled. At some point later, commit8ca3f6c382("Allow selection of all defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450 family without further justification. We have since the year 2011 [1] been unable to run OpenBIOS in the 7450s and have not heard of any other software that is used with those CPUs in QEMU. Attempts were made to find a guest OS that implemented the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS 3.15. All CPUs that registered this feature were moved to an MMU model that replaces the software TLB with a QEMU hardware TLB implementation. They can now run the same software as the 7400 CPUs, including the OSes mentioned above. References: - https://bugs.launchpad.net/qemu/+bug/812398 https://gitlab.com/qemu-project/qemu/-/issues/86 - https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html message id: 20211119134431.406753-1-farosas@linux.ibm.com Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211130230123.781844-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
230 lines
7.9 KiB
C
230 lines
7.9 KiB
C
/*
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* QEMU PowerPC CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef QEMU_PPC_CPU_QOM_H
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#define QEMU_PPC_CPU_QOM_H
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#include "hw/core/cpu.h"
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#include "qom/object.h"
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#ifdef TARGET_PPC64
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#define TYPE_POWERPC_CPU "powerpc64-cpu"
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#else
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#define TYPE_POWERPC_CPU "powerpc-cpu"
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#endif
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OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
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POWERPC_CPU)
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typedef struct CPUPPCState CPUPPCState;
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typedef struct ppc_tb_t ppc_tb_t;
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typedef struct ppc_dcr_t ppc_dcr_t;
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/*****************************************************************************/
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/* MMU model */
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typedef enum powerpc_mmu_t powerpc_mmu_t;
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enum powerpc_mmu_t {
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POWERPC_MMU_UNKNOWN = 0x00000000,
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/* Standard 32 bits PowerPC MMU */
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POWERPC_MMU_32B = 0x00000001,
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/* PowerPC 6xx MMU with software TLB */
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POWERPC_MMU_SOFT_6xx = 0x00000002,
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/*
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* PowerPC 74xx MMU with software TLB (this has been
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* disabled, see git history for more information.
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* keywords: tlbld tlbli TLBMISS PTEHI PTELO)
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*/
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POWERPC_MMU_SOFT_74xx = 0x00000003,
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/* PowerPC 4xx MMU with software TLB */
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POWERPC_MMU_SOFT_4xx = 0x00000004,
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/* PowerPC 4xx MMU with software TLB and zones protections */
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POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
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/* PowerPC MMU in real mode only */
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POWERPC_MMU_REAL = 0x00000006,
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/* Freescale MPC8xx MMU model */
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POWERPC_MMU_MPC8xx = 0x00000007,
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/* BookE MMU model */
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POWERPC_MMU_BOOKE = 0x00000008,
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/* BookE 2.06 MMU model */
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POWERPC_MMU_BOOKE206 = 0x00000009,
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/* PowerPC 601 MMU model (specific BATs format) */
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POWERPC_MMU_601 = 0x0000000A,
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#define POWERPC_MMU_64 0x00010000
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/* 64 bits PowerPC MMU */
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POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
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/* Architecture 2.03 and later (has LPCR) */
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POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
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/* Architecture 2.06 variant */
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POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
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/* Architecture 2.07 variant */
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POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
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/* Architecture 3.00 variant */
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POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
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};
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static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
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{
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return mmu_model & POWERPC_MMU_64;
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}
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/*****************************************************************************/
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/* Exception model */
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typedef enum powerpc_excp_t powerpc_excp_t;
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enum powerpc_excp_t {
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POWERPC_EXCP_UNKNOWN = 0,
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/* Standard PowerPC exception model */
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POWERPC_EXCP_STD,
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/* PowerPC 40x exception model */
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POWERPC_EXCP_40x,
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/* PowerPC 601 exception model */
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POWERPC_EXCP_601,
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/* PowerPC 602 exception model */
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POWERPC_EXCP_602,
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/* PowerPC 603 exception model */
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POWERPC_EXCP_603,
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/* PowerPC 603e exception model */
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POWERPC_EXCP_603E,
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/* PowerPC G2 exception model */
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POWERPC_EXCP_G2,
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/* PowerPC 604 exception model */
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POWERPC_EXCP_604,
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/* PowerPC 7x0 exception model */
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POWERPC_EXCP_7x0,
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/* PowerPC 7x5 exception model */
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POWERPC_EXCP_7x5,
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/* PowerPC 74xx exception model */
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POWERPC_EXCP_74xx,
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/* BookE exception model */
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POWERPC_EXCP_BOOKE,
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/* PowerPC 970 exception model */
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POWERPC_EXCP_970,
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/* POWER7 exception model */
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POWERPC_EXCP_POWER7,
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/* POWER8 exception model */
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POWERPC_EXCP_POWER8,
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/* POWER9 exception model */
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POWERPC_EXCP_POWER9,
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/* POWER10 exception model */
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POWERPC_EXCP_POWER10,
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};
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/*****************************************************************************/
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/* PM instructions */
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typedef enum {
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PPC_PM_DOZE,
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PPC_PM_NAP,
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PPC_PM_SLEEP,
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PPC_PM_RVWINKLE,
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PPC_PM_STOP,
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} powerpc_pm_insn_t;
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/*****************************************************************************/
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/* Input pins model */
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typedef enum powerpc_input_t powerpc_input_t;
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enum powerpc_input_t {
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PPC_FLAGS_INPUT_UNKNOWN = 0,
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/* PowerPC 6xx bus */
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PPC_FLAGS_INPUT_6xx,
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/* BookE bus */
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PPC_FLAGS_INPUT_BookE,
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/* PowerPC 405 bus */
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PPC_FLAGS_INPUT_405,
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/* PowerPC 970 bus */
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PPC_FLAGS_INPUT_970,
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/* PowerPC POWER7 bus */
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PPC_FLAGS_INPUT_POWER7,
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/* PowerPC POWER9 bus */
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PPC_FLAGS_INPUT_POWER9,
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/* PowerPC 401 bus */
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PPC_FLAGS_INPUT_401,
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/* Freescale RCPU bus */
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PPC_FLAGS_INPUT_RCPU,
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};
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typedef struct PPCHash64Options PPCHash64Options;
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/**
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* PowerPCCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A PowerPC CPU model.
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*/
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struct PowerPCCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceUnrealize parent_unrealize;
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DeviceReset parent_reset;
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void (*parent_parse_features)(const char *type, char *str, Error **errp);
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uint32_t pvr;
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bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
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uint64_t pcr_mask; /* Available bits in PCR register */
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uint64_t pcr_supported; /* Bits for supported PowerISA versions */
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uint32_t svr;
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uint64_t insns_flags;
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uint64_t insns_flags2;
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uint64_t msr_mask;
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uint64_t lpcr_mask; /* Available bits in the LPCR */
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uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
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powerpc_mmu_t mmu_model;
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powerpc_excp_t excp_model;
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powerpc_input_t bus_model;
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uint32_t flags;
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int bfd_mach;
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uint32_t l1_dcache_size, l1_icache_size;
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#ifndef CONFIG_USER_ONLY
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unsigned int gdb_num_sprs;
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const char *gdb_spr_xml;
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#endif
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const PPCHash64Options *hash64_opts;
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struct ppc_radix_page_info *radix_page_info;
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uint32_t lrg_decr_bits;
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int n_host_threads;
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void (*init_proc)(CPUPPCState *env);
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int (*check_pow)(CPUPPCState *env);
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};
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#ifndef CONFIG_USER_ONLY
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typedef struct PPCTimebase {
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uint64_t guest_timebase;
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int64_t time_of_the_day_ns;
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bool runstate_paused;
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} PPCTimebase;
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extern const VMStateDescription vmstate_ppc_timebase;
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#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
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.name = (stringify(_field)), \
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.version_id = (_version), \
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.size = sizeof(PPCTimebase), \
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.vmsd = &vmstate_ppc_timebase, \
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.flags = VMS_STRUCT, \
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.offset = vmstate_offset_value(_state, _field, PPCTimebase), \
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}
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void cpu_ppc_clock_vm_state_change(void *opaque, bool running,
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RunState state);
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#endif
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#endif
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