qemu-e2k/tcg/riscv
Richard Henderson d46259c037 tcg: Split out tcg-target-reg-bits.h
Often, the only thing we need to know about the TCG host
is the register size.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05 12:04:28 -07:00
..
tcg-target-con-set.h tcg/riscv: Support CTZ, CLZ from Zbb 2023-05-25 15:29:36 +00:00
tcg-target-con-str.h tcg/riscv: Support ANDN, ORN, XNOR from Zbb 2023-05-25 13:57:52 +00:00
tcg-target-reg-bits.h tcg: Split out tcg-target-reg-bits.h 2023-06-05 12:04:28 -07:00
tcg-target.c.inc tcg: Add tlb_fast_offset to TCGContext 2023-06-05 12:04:28 -07:00
tcg-target.h tcg: Split out tcg-target-reg-bits.h 2023-06-05 12:04:28 -07:00