Stephen Long a5421b54c4 target/arm: Implement SVE2 bitwise shift immediate ... Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-81-richard.henderson@linaro.org Message-Id: <20200430194159.24064-1-steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-05-25 16:01:44 +01:00
..
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
cpu64.c	target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type	2021-05-25 16:01:43 +01:00
cpu_tcg.c
cpu-param.h
cpu-qom.h
cpu.c	Do not include sysemu/sysemu.h if it's not really necessary	2021-05-02 17:24:50 +02:00
cpu.h	target/arm: Implement SVE2 crypto constructive binary operations	2021-05-25 16:01:44 +01:00
crypto_helper.c
debug_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper-sve.h	target/arm: Implement SVE2 bitwise shift immediate	2021-05-25 16:01:44 +01:00
helper.c	target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2	2021-05-25 16:01:43 +01:00
helper.h	target/arm: Implement SVE mixed sign dot product	2021-05-25 16:01:44 +01:00
idau.h
internals.h
iwmmxt_helper.c
kvm64.c	target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2	2021-05-25 16:01:43 +01:00
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
m_helper.c	target/arm: Use correct SP in M-profile exception return	2021-05-25 16:01:43 +01:00
m-nocp.decode
machine.c
meson.build	target/arm: Make translate-neon.c.inc its own compilation unit	2021-05-10 13:24:09 +01:00
monitor.c
mte_helper.c
neon_helper.c	target/arm: Split out saturating/rounding shifts from neon	2021-05-25 16:01:43 +01:00
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_addsub.h
op_helper.c	target/arm: Make WFI a NOP for userspace emulators	2021-05-10 13:24:09 +01:00
pauth_helper.c
psci.c
sve_helper.c	target/arm: Implement SVE2 bitwise shift immediate	2021-05-25 16:01:44 +01:00
sve.decode	target/arm: Implement SVE2 bitwise shift immediate	2021-05-25 16:01:44 +01:00
syndrome.h
t16.decode
t32.decode
tlb_helper.c
trace-events
trace.h
translate-a32.h	target/arm: Make translate-neon.c.inc its own compilation unit	2021-05-10 13:24:09 +01:00
translate-a64.c	target/arm: Pass separate addend to FCMLA helpers	2021-05-25 16:01:44 +01:00
translate-a64.h	target/arm: Implement SVE2 XAR	2021-05-25 16:01:44 +01:00
translate-m-nocp.c	target/arm: Split m-nocp trans functions into their own file	2021-05-10 13:24:09 +01:00
translate-neon.c	target/arm: Pass separate addend to FCMLA helpers	2021-05-25 16:01:44 +01:00
translate-sve.c	target/arm: Implement SVE2 bitwise shift immediate	2021-05-25 16:01:44 +01:00
translate-vfp.c	target/arm: Make translate-vfp.c.inc its own compilation unit	2021-05-10 13:24:09 +01:00
translate.c	target/arm: Make sure that commpage's tb->size != 0	2021-05-20 14:19:30 +02:00
translate.h	target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h	2021-05-10 13:24:09 +01:00
vec_helper.c	target/arm: Implement SVE mixed sign dot product	2021-05-25 16:01:44 +01:00
vec_internal.h	target/arm: Implement SVE2 complex integer multiply-add	2021-05-25 16:01:44 +01:00
vfp_helper.c
vfp-uncond.decode
vfp.decode