OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity
qemu-e2k/target/riscv
History
Richard Henderson a120d32097 include/exec: Implement cpu_mmu_index generically 
For user-only mode, use MMU_USER_IDX.
For system mode, use CPUClass.mmu_index.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03 16:46:10 +10:00
..
insn_trans
target/riscv: Add support for Zacas extension
2024-01-10 18:47:47 +10:00
kvm
target/riscv/kvm: add RVV and Vector CSR regs
2024-01-10 18:47:47 +10:00
tcg
include/qemu: Add TCGCPUOps typedef to typedefs.h
2024-01-29 21:04:10 +10:00
arch_dump.c
target/riscv: Fix format for comments
2023-05-05 10:49:50 +10:00
bitmanip_helper.c
…
common-semi-target.h
…
cpu_bits.h
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
2023-11-07 11:02:17 +10:00
cpu_cfg.h
target/riscv: implement svade
2024-01-10 18:47:47 +10:00
cpu_helper.c
target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index
2024-02-03 16:46:10 +10:00
cpu_user.h
…
cpu_vendorid.h
target/riscv: add Ventana's Veyron V1 CPU
2023-05-05 10:49:50 +10:00
cpu-param.h
…
cpu-qom.h
target/riscv: add rva22s64 cpu
2024-01-10 18:47:47 +10:00
cpu.c
target/riscv: Populate CPUClass.mmu_index
2024-02-03 16:46:10 +10:00
cpu.h
include/exec: Implement cpu_mmu_index generically
2024-02-03 16:46:10 +10:00
crypto_helper.c
target/riscv: Use accelerated helper for AES64KS1I
2023-09-11 11:45:55 +10:00
csr.c
target/riscv: Assert that the CSR numbers will be correct
2024-01-10 18:47:47 +10:00
debug.c
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
debug.h
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
fpu_helper.c
riscv: Add support for the Zfa extension
2023-07-10 22:29:20 +10:00
gdbstub.c
target/riscv: rename ext_icsr to ext_zicsr
2023-11-07 11:02:17 +10:00
helper.h
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
insn16.decode
target/riscv: add support for Zcmt extension
2023-05-05 10:49:50 +10:00
insn32.decode
target/riscv: Add support for Zacas extension
2024-01-10 18:47:47 +10:00
instmap.h
…
internals.h
target/riscv: Use env_archcpu() in [check_]nanbox()
2023-11-07 12:13:27 +01:00
Kconfig
…
m128_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
machine.c
target/riscv: Constify VMState in machine.c
2023-12-29 11:17:30 +11:00
meson.build
target/riscv: move KVM only files to kvm subdir
2023-10-12 12:20:24 +10:00
monitor.c
riscv: spelling fixes
2023-09-08 13:08:52 +03:00
op_helper.c
target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index
2024-02-03 16:46:10 +10:00
pmp.c
target/riscv: pmp: Ignore writes when RW=01 and MML=0
2024-01-10 18:47:47 +10:00
pmp.h
target/riscv/pmp: Use hwaddr instead of target_ulong for RV32
2024-01-10 18:47:46 +10:00
pmu.c
target/riscv: Add "pmu-mask" property to replace "pmu-num"
2023-11-07 11:06:02 +10:00
pmu.h
target/riscv: Use existing PMU counter mask in FDT generation
2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c
riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
2024-01-10 18:47:47 +10:00
sbi_ecall_interface.h
target/riscv: Fix format for comments
2023-05-05 10:49:50 +10:00
time_helper.c
target/riscv: Simplify type conversion for CPURISCVState
2023-05-05 10:49:49 +10:00
time_helper.h
target/riscv: Simplify type conversion for CPURISCVState
2023-05-05 10:49:49 +10:00
trace-events
…
trace.h
…
translate.c
target: Use vaddr in gen_intermediate_code
2024-01-29 07:06:03 +10:00
vcrypto_helper.c
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
vector_helper.c
target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index
2024-02-03 16:46:10 +10:00
vector_internals.c
riscv: Clean up includes
2024-01-30 21:20:20 +03:00
vector_internals.h
riscv: Clean up includes
2024-01-30 21:20:20 +03:00
xthead.decode
…
XVentanaCondOps.decode
…
zce_helper.c
target/riscv: add support for Zcmt extension
2023-05-05 10:49:50 +10:00