423f0742a8
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2846 c046a42c-6fe2-441c-8c8c-71466251a162
308 lines
7.9 KiB
C
308 lines
7.9 KiB
C
/*
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* ARM PrimeCell Timer modules.
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*
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* Copyright (c) 2005-2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "vl.h"
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#include "arm_pic.h"
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/* Common timer implementation. */
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#define TIMER_CTRL_ONESHOT (1 << 0)
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#define TIMER_CTRL_32BIT (1 << 1)
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#define TIMER_CTRL_DIV1 (0 << 2)
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#define TIMER_CTRL_DIV16 (1 << 2)
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#define TIMER_CTRL_DIV256 (2 << 2)
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#define TIMER_CTRL_IE (1 << 5)
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#define TIMER_CTRL_PERIODIC (1 << 6)
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#define TIMER_CTRL_ENABLE (1 << 7)
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typedef struct {
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ptimer_state *timer;
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uint32_t control;
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uint32_t limit;
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int freq;
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int int_level;
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qemu_irq irq;
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} arm_timer_state;
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/* Check all active timers, and schedule the next timer interrupt. */
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static void arm_timer_update(arm_timer_state *s)
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{
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/* Update interrupts. */
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if (s->int_level && (s->control & TIMER_CTRL_IE)) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
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{
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arm_timer_state *s = (arm_timer_state *)opaque;
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switch (offset >> 2) {
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case 0: /* TimerLoad */
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case 6: /* TimerBGLoad */
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return s->limit;
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case 1: /* TimerValue */
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return ptimer_get_count(s->timer);
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case 2: /* TimerControl */
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return s->control;
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case 4: /* TimerRIS */
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return s->int_level;
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case 5: /* TimerMIS */
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if ((s->control & TIMER_CTRL_IE) == 0)
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return 0;
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return s->int_level;
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default:
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cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
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(int)offset);
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return 0;
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}
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}
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/* Reset the timer limit after settings have changed. */
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static void arm_timer_recalibrate(arm_timer_state *s, int reload)
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{
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uint32_t limit;
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if ((s->control & TIMER_CTRL_PERIODIC) == 0) {
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/* Free running. */
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if (s->control & TIMER_CTRL_32BIT)
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limit = 0xffffffff;
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else
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limit = 0xffff;
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} else {
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/* Periodic. */
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limit = s->limit;
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}
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ptimer_set_limit(s->timer, limit, reload);
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}
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static void arm_timer_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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arm_timer_state *s = (arm_timer_state *)opaque;
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int freq;
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switch (offset >> 2) {
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case 0: /* TimerLoad */
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s->limit = value;
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arm_timer_recalibrate(s, 1);
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break;
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case 1: /* TimerValue */
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/* ??? Linux seems to want to write to this readonly register.
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Ignore it. */
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break;
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case 2: /* TimerControl */
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if (s->control & TIMER_CTRL_ENABLE) {
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/* Pause the timer if it is running. This may cause some
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inaccuracy dure to rounding, but avoids a whole lot of other
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messyness. */
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ptimer_stop(s->timer);
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}
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s->control = value;
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freq = s->freq;
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/* ??? Need to recalculate expiry time after changing divisor. */
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switch ((value >> 2) & 3) {
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case 1: freq >>= 4; break;
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case 2: freq >>= 8; break;
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}
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arm_timer_recalibrate(s, 0);
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ptimer_set_freq(s->timer, freq);
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if (s->control & TIMER_CTRL_ENABLE) {
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/* Restart the timer if still enabled. */
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ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
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}
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break;
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case 3: /* TimerIntClr */
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s->int_level = 0;
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break;
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case 6: /* TimerBGLoad */
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s->limit = value;
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arm_timer_recalibrate(s, 0);
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break;
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default:
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cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",
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(int)offset);
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}
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arm_timer_update(s);
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}
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static void arm_timer_tick(void *opaque)
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{
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arm_timer_state *s = (arm_timer_state *)opaque;
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s->int_level = 1;
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arm_timer_update(s);
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}
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static void *arm_timer_init(uint32_t freq, qemu_irq irq)
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{
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arm_timer_state *s;
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QEMUBH *bh;
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s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
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s->irq = irq;
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s->freq = freq;
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s->control = TIMER_CTRL_IE;
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bh = qemu_bh_new(arm_timer_tick, s);
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s->timer = ptimer_init(bh);
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/* ??? Save/restore. */
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return s;
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}
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/* ARM PrimeCell SP804 dual timer module.
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Docs for this device don't seem to be publicly available. This
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implementation is based on guesswork, the linux kernel sources and the
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Integrator/CP timer modules. */
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typedef struct {
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void *timer[2];
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int level[2];
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uint32_t base;
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qemu_irq irq;
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} sp804_state;
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/* Merge the IRQs from the two component devices. */
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static void sp804_set_irq(void *opaque, int irq, int level)
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{
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sp804_state *s = (sp804_state *)opaque;
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s->level[irq] = level;
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qemu_set_irq(s->irq, s->level[0] || s->level[1]);
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}
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static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
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{
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sp804_state *s = (sp804_state *)opaque;
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/* ??? Don't know the PrimeCell ID for this device. */
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offset -= s->base;
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if (offset < 0x20) {
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return arm_timer_read(s->timer[0], offset);
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} else {
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return arm_timer_read(s->timer[1], offset - 0x20);
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}
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}
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static void sp804_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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sp804_state *s = (sp804_state *)opaque;
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offset -= s->base;
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if (offset < 0x20) {
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arm_timer_write(s->timer[0], offset, value);
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} else {
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arm_timer_write(s->timer[1], offset - 0x20, value);
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}
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}
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static CPUReadMemoryFunc *sp804_readfn[] = {
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sp804_read,
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sp804_read,
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sp804_read
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};
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static CPUWriteMemoryFunc *sp804_writefn[] = {
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sp804_write,
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sp804_write,
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sp804_write
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};
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void sp804_init(uint32_t base, qemu_irq irq)
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{
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int iomemtype;
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sp804_state *s;
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qemu_irq *qi;
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s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
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qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
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s->base = base;
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s->irq = irq;
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/* ??? The timers are actually configurable between 32kHz and 1MHz, but
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we don't implement that. */
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s->timer[0] = arm_timer_init(1000000, qi[0]);
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s->timer[1] = arm_timer_init(1000000, qi[1]);
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iomemtype = cpu_register_io_memory(0, sp804_readfn,
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sp804_writefn, s);
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cpu_register_physical_memory(base, 0x00000fff, iomemtype);
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/* ??? Save/restore. */
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}
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/* Integrator/CP timer module. */
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typedef struct {
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void *timer[3];
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uint32_t base;
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} icp_pit_state;
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static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
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{
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icp_pit_state *s = (icp_pit_state *)opaque;
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int n;
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/* ??? Don't know the PrimeCell ID for this device. */
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offset -= s->base;
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n = offset >> 8;
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if (n > 3)
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cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
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return arm_timer_read(s->timer[n], offset & 0xff);
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}
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static void icp_pit_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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icp_pit_state *s = (icp_pit_state *)opaque;
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int n;
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offset -= s->base;
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n = offset >> 8;
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if (n > 3)
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cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
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arm_timer_write(s->timer[n], offset & 0xff, value);
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}
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static CPUReadMemoryFunc *icp_pit_readfn[] = {
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icp_pit_read,
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icp_pit_read,
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icp_pit_read
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};
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static CPUWriteMemoryFunc *icp_pit_writefn[] = {
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icp_pit_write,
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icp_pit_write,
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icp_pit_write
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};
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void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
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{
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int iomemtype;
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icp_pit_state *s;
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s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
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s->base = base;
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/* Timer 0 runs at the system clock speed (40MHz). */
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s->timer[0] = arm_timer_init(40000000, pic[irq]);
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/* The other two timers run at 1MHz. */
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s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);
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s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);
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iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
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icp_pit_writefn, s);
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cpu_register_physical_memory(base, 0x00000fff, iomemtype);
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/* ??? Save/restore. */
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}
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