Yifei Jiang 33a9a57d2c target/riscv: raise exception to HS-mode at get_physical_address ... VS-stage translation at get_physical_address needs to translate pte address by G-stage translation. But the G-stage translation error can not be distinguished from VS-stage translation error in riscv_cpu_tlb_fill. On migration, destination needs to rebuild pte, and this G-stage translation error must be handled by HS-mode. So introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could distinguish and raise it to HS-mode. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201014101728.848-1-jiangyifei@huawei.com [ Change by AF: - Clarify the fault_pte_addr shift ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-10-22 12:00:22 -07:00
..
insn_trans	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
cpu_bits.h	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
cpu_helper.c	target/riscv: raise exception to HS-mode at get_physical_address	2020-10-22 12:00:22 -07:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Set instance_align on RISCVCPU TypeInfo	2020-09-18 13:59:51 -04:00
cpu.h	target/riscv: raise exception to HS-mode at get_physical_address	2020-10-22 12:00:22 -07:00
csr.c	icount: rename functions to be consistent with the module name	2020-10-05 16:41:22 +02:00
fpu_helper.c
gdbstub.c
helper.h	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
instmap.h
internals.h
meson.build
monitor.c
op_helper.c	target/riscv: Fix implementation of HLVX.WU instruction	2020-10-22 12:00:22 -07:00
pmp.c
pmp.h
trace-events	trace-events: Fix attribution of trace points to source	2020-09-09 17:17:58 +01:00
trace.h
translate.c	target/riscv: Update the Hypervisor trap return/entry	2020-08-25 09:11:36 -07:00
vector_helper.c	softfloat: Implement the full set of comparisons for float16	2020-08-28 10:48:07 -07:00