qemu-e2k/target/riscv
Jonathan Behrens ab9056ff9b
target/riscv: Expose "priv" register for GDB for reads
This patch enables a debugger to read the current privilege level via a virtual
"priv" register. When compiled with CONFIG_USER_ONLY the register is still
visible but always reports the value zero.

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28 07:47:29 -07:00
..
insn_trans tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
cpu_bits.h target/riscv: Update the Hypervisor CSRs to v0.4 2019-09-17 08:42:43 -07:00
cpu_helper.c linux-user/riscv: Propagate fault address 2019-10-28 07:47:27 -07:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu.c RISC-V: Implement cpu_do_transaction_failed 2019-10-28 07:47:27 -07:00
cpu.h RISC-V: Implement cpu_do_transaction_failed 2019-10-28 07:47:27 -07:00
csr.c riscv: Skip checking CSR privilege level in debugger mode 2019-10-28 07:46:53 -07:00
fpu_helper.c target/riscv: rationalise softfloat includes 2019-08-19 12:07:13 +01:00
gdbstub.c target/riscv: Expose "priv" register for GDB for reads 2019-10-28 07:47:29 -07:00
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h Supply missing header guards 2019-06-12 13:20:21 +02:00
Makefile.objs riscv: hmp: Add a command to show virtual memory mappings 2019-09-17 08:42:43 -07:00
monitor.c riscv: hmp: Add a command to show virtual memory mappings 2019-09-17 08:42:43 -07:00
op_helper.c target/riscv: Use env_cpu, env_archcpu 2019-06-10 07:03:42 -07:00
pmp.c target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events 2019-09-17 08:42:42 -07:00
pmp.h RISC-V: Check for the effective memory privilege mode during PMP checks 2019-06-23 23:44:41 -07:00
trace-events target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events 2019-09-17 08:42:42 -07:00
translate.c target/riscv: Remove redundant declaration pragmas 2019-08-19 08:13:14 -07:00