0abaa41d93
Bug fix: * Some guests may crash when using "-cpu host" due to TOPOEXT, disable it by default Features: * PV_SEND_IPI feature bit * Icelake-{Server,Client} CPU models * New CPUID feature bits: PV_SEND_IPI, WBNOINVD, PCONFIG, ARCH_CAPABILITIES Documentation: * docs/qemu-cpu-models.texi -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJbdiXVAAoJECgHk2+YTcWmcuUP/i1ekHKIm1Irfelhbd0CpGJj GTUoK/EAkNXxUq5qYpNL23sElxCyduoFlyrpHMxdRmaffrw7EBg/ye3eZNT9SMcE OL2iLohZhev4V9iO2lBx4/4awFxHJC8vx9q4OQXHXewNZxoFdi+6h+b7eDnSD1XO 1saCSem5bZtu6Ra/aco21SVW7afWOPtYAW0Z6fXJ040K4wgKdxGo2NfBkRX1SUMD xqUG084FJht+MeIq95mcY9bSubg9fXKYUr6psE2mL+ycztbx+vnUMMS+Yj8XfuCC QIBzlpF0ZCTZlxRsmQqW/ZBb5qsSdJiCMGPibeLl3vKzByZ5NpZk4xUw69NcwQ07 kAEhK3Ug4X+gjUtLH3QvRF7pIHOtJS5RdHpEfOBYZ/P+JfX7y2tCmqlAhPje6urf av2Go4PvdD8gS0KO4bpasE6guLz+bp734xcA9c/pVwWITOT8xBG9XGqj1cZ4/S+b uJWLdeeR6vspJBs3BjWxxCMcAS3tk8CzYamjJBYnPasXznnEnmwaS8X5QWCS0h1R Hx83z9WGr4oPry7Pg0keKEBFA2FvFtYH/xbSBUOpiaGvDICPY8w7BfOCtjBNxOsm wMtlx6fBsXv89ymWpYHCldvdMw7sF6GGYuQIBnF7BqXKgLZABcOKRXG/JfVdK5iU QxoROA+kpgws7LK3lRUV =uE8w -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging x86 queue, 2018-08-16 Bug fix: * Some guests may crash when using "-cpu host" due to TOPOEXT, disable it by default Features: * PV_SEND_IPI feature bit * Icelake-{Server,Client} CPU models * New CPUID feature bits: PV_SEND_IPI, WBNOINVD, PCONFIG, ARCH_CAPABILITIES Documentation: * docs/qemu-cpu-models.texi # gpg: Signature made Fri 17 Aug 2018 02:33:09 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Disable TOPOEXT by default on "-cpu host" target-i386: adds PV_SEND_IPI CPUID feature bit i386: Add new CPU model Icelake-{Server,Client} i386: Add CPUID bit for WBNOINVD i386: Add CPUID bit for PCONFIG i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES docs: add guidance on configuring CPU models for x86 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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alpha | ||
arm | ||
cris | ||
hppa | ||
i386 | ||
lm32 | ||
m68k | ||
microblaze | ||
mips | ||
moxie | ||
nios2 | ||
openrisc | ||
ppc | ||
riscv | ||
s390x | ||
sh4 | ||
sparc | ||
tilegx | ||
tricore | ||
unicore32 | ||
xtensa |