42fc73a1ce
On the MIPS Magnum, the time that is held in the RTC's NVRAM should be relative to midnight on 1980-01-01. This patch adds an extra parameter to rtc_init(), allowing different epochs to be used. For the Magnum, 1980 is specified, and for all other machines, 2000 is specified. I've not modified the handling of the century byte, as with an epoch of 1980 and a year of 2009, one could argue that it should hold either 0, 1, 19 or 20. NT 3.50 on MIPS does not read the century byte. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6429 c046a42c-6fe2-441c-8c8c-71466251a162
167 lines
5.4 KiB
C
167 lines
5.4 KiB
C
#ifndef HW_PC_H
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#define HW_PC_H
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/* PC-style peripherals (also used by other machines). */
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/* serial.c */
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SerialState *serial_init(int base, qemu_irq irq, int baudbase,
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CharDriverState *chr);
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SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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qemu_irq irq, int baudbase,
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CharDriverState *chr, int ioregister);
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uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
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void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
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uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
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void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
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uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
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void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
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/* parallel.c */
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typedef struct ParallelState ParallelState;
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ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
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ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
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/* i8259.c */
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typedef struct PicState2 PicState2;
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extern PicState2 *isa_pic;
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void pic_set_irq(int irq, int level);
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void pic_set_irq_new(void *opaque, int irq, int level);
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qemu_irq *i8259_init(qemu_irq parent_irq);
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void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
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void *alt_irq_opaque);
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int pic_read_irq(PicState2 *s);
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void pic_update_irq(PicState2 *s);
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uint32_t pic_intack_read(PicState2 *s);
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void pic_info(void);
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void irq_info(void);
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/* APIC */
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typedef struct IOAPICState IOAPICState;
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int apic_init(CPUState *env);
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int apic_accept_pic_intr(CPUState *env);
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void apic_deliver_pic_intr(CPUState *env, int level);
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int apic_get_interrupt(CPUState *env);
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IOAPICState *ioapic_init(void);
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void ioapic_set_irq(void *opaque, int vector, int level);
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void apic_reset_irq_delivered(void);
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int apic_get_irq_delivered(void);
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/* i8254.c */
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#define PIT_FREQ 1193182
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typedef struct PITState PITState;
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PITState *pit_init(int base, qemu_irq irq);
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void pit_set_gate(PITState *pit, int channel, int val);
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int pit_get_gate(PITState *pit, int channel);
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int pit_get_initial_count(PITState *pit, int channel);
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int pit_get_mode(PITState *pit, int channel);
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int pit_get_out(PITState *pit, int channel, int64_t current_time);
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void hpet_pit_disable(void);
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void hpet_pit_enable(void);
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/* vmport.c */
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void vmport_init(void);
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void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
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/* vmmouse.c */
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void *vmmouse_init(void *m);
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/* pckbd.c */
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void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
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void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
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target_phys_addr_t base, ram_addr_t size,
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target_phys_addr_t mask);
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/* mc146818rtc.c */
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typedef struct RTCState RTCState;
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RTCState *rtc_init(int base, qemu_irq irq, int base_year);
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RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
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int base_year);
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void rtc_set_memory(RTCState *s, int addr, int val);
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void rtc_set_date(RTCState *s, const struct tm *tm);
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void cmos_set_s3_resume(void);
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/* pc.c */
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extern int fd_bootchk;
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void ioport_set_a20(int enable);
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int ioport_get_a20(void);
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/* acpi.c */
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extern int acpi_enabled;
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq);
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void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
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void acpi_bios_init(void);
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/* hpet.c */
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extern int no_hpet;
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/* pcspk.c */
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void pcspk_init(PITState *);
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int pcspk_audio_init(AudioState *, qemu_irq *pic);
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/* piix_pci.c */
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PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
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void i440fx_set_smm(PCIDevice *d, int val);
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int piix3_init(PCIBus *bus, int devfn);
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void i440fx_init_memory_mappings(PCIDevice *d);
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extern PCIDevice *piix4_dev;
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int piix4_init(PCIBus *bus, int devfn);
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/* vga.c */
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enum vga_retrace_method {
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VGA_RETRACE_DUMB,
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VGA_RETRACE_PRECISE
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};
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extern enum vga_retrace_method vga_retrace_method;
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#ifndef TARGET_SPARC
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#define VGA_RAM_SIZE (8192 * 1024)
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#else
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#define VGA_RAM_SIZE (9 * 1024 * 1024)
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#endif
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int isa_vga_init(uint8_t *vga_ram_base,
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unsigned long vga_ram_offset, int vga_ram_size);
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int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
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unsigned long vga_ram_offset, int vga_ram_size,
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unsigned long vga_bios_offset, int vga_bios_size);
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int isa_vga_mm_init(uint8_t *vga_ram_base,
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unsigned long vga_ram_offset, int vga_ram_size,
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target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
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int it_shift);
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/* cirrus_vga.c */
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void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
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ram_addr_t vga_ram_offset, int vga_ram_size);
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void isa_cirrus_vga_init(uint8_t *vga_ram_base,
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ram_addr_t vga_ram_offset, int vga_ram_size);
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/* ide.c */
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void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
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BlockDriverState *hd0, BlockDriverState *hd1);
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void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
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int secondary_ide_enabled);
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void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
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qemu_irq *pic);
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void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
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qemu_irq *pic);
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/* ne2000.c */
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void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
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#endif
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