qemu-e2k/target/riscv
Bin Meng b4cb178efb target/riscv: pmp: Fix some typos
%s/CSP/CSR
%s/thie/the

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-07-15 08:56:00 +10:00
..
insn_trans target/riscv: rvb: add/shift with prefix zero-extend 2021-06-08 09:59:45 +10:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: rvb: generalized or-combine 2021-06-08 09:59:45 +10:00
cpu_bits.h target/riscv: fix wfi exception behavior 2021-06-08 09:59:42 +10:00
cpu_helper.c target/riscv: Remove the hardcoded SATP_MODE macro 2021-05-11 20:02:07 +10:00
cpu_user.h
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c target/riscv: rvb: add b-ext version cpu option 2021-06-08 09:59:46 +10:00
cpu.h target/riscv: rvb: add b-ext version cpu option 2021-06-08 09:59:46 +10:00
csr.c target/riscv: Remove the hardcoded SATP_MODE macro 2021-05-11 20:02:07 +10:00
fpu_helper.c target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
gdbstub.c target/riscv: gdbstub: Fix dynamic CSR XML generation 2021-06-24 05:00:12 -07:00
helper.h target/riscv: rvb: generalized or-combine 2021-06-08 09:59:45 +10:00
insn16.decode target/riscv: Consolidate RV32/64 16-bit instructions 2021-05-11 20:02:07 +10:00
insn32.decode target/riscv: rvb: add/shift with prefix zero-extend 2021-06-08 09:59:45 +10:00
instmap.h
internals.h
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
machine.c target/riscv: Remove privilege v1.9 specific CSR related code 2021-05-11 20:01:10 +10:00
meson.build target/riscv: rvb: generalized reverse 2021-06-08 09:59:45 +10:00
monitor.c target/riscv: Remove the hardcoded SATP_MODE macro 2021-05-11 20:02:07 +10:00
op_helper.c target/riscv: fix wfi exception behavior 2021-06-08 09:59:42 +10:00
pmp.c target/riscv: pmp: Fix some typos 2021-07-15 08:56:00 +10:00
pmp.h target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h
translate.c target/riscv: Use translator_use_goto_tb 2021-07-09 09:42:28 -07:00
vector_helper.c target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00