qemu-e2k/disas
Christoph Müllner 36df75a0a9 riscv/disas: Fix disas output of upper immediates
The GNU assembler produces the following output for instructions
with upper immediates:
    00002597                auipc   a1,0x2
    000024b7                lui     s1,0x2
    6409                    lui     s0,0x2 # c.lui

The immediate operands of upper immediates are not shifted.

However, the QEMU disassembler prints them shifted:
    00002597          auipc                   a1,8192
    000024b7          lui                     s1,8192
    6409              lui                     s0,8192 # c.lui

The current implementation extracts the immediate bits and shifts the by 12,
so the internal representation of the immediate is the actual immediate.
However, the immediates are later printed using rv_fmt_rd_imm or
rv_fmt_rd_offset, which don't undo the shift.

Let's fix this by using specific output formats for instructions
with upper immediates, that take care of the shift.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230711075051.1531007-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-19 14:30:04 +10:00
..
alpha.c
capstone.c
cris.c
disas-internal.h disas: Move softmmu specific code to separate file 2023-05-11 09:49:55 +01:00
disas-mon.c disas: Move softmmu specific code to separate file 2023-05-11 09:49:55 +01:00
disas.c disas: Move disas.c into the target-independent source set 2023-05-11 09:51:07 +01:00
hexagon.c
hppa.c
m68k.c
meson.build disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
microblaze.c
mips.c disas/mips: Fix branch displacement for BEQZC and BNEZC 2022-10-31 11:32:07 +01:00
nanomips.c disas/nanomips: Tidy read for 48-bit opcodes 2022-11-08 01:04:25 +01:00
nios2.c
riscv-xthead.c disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
riscv-xthead.h disas/riscv: Add support for XThead* instructions 2023-07-10 22:29:14 +10:00
riscv-xventana.c disas/riscv: Add support for XVentanaCondOps 2023-07-10 22:29:14 +10:00
riscv-xventana.h disas/riscv: Add support for XVentanaCondOps 2023-07-10 22:29:14 +10:00
riscv.c riscv/disas: Fix disas output of upper immediates 2023-07-19 14:30:04 +10:00
riscv.h riscv/disas: Fix disas output of upper immediates 2023-07-19 14:30:04 +10:00
sh4.c
sparc.c
xtensa.c