qemu-e2k/target-arm
Alex Bennée bc242f9bb6 target-arm: A64: Implement floating point pairwise insns
Add support for the floating-point pairwise operations
FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the
code which was previously handling only integer pairwise operations,
and push the integer-specific decode and handling of unallocated
cases up one level in the call tree, so we can also call it from
the floating-point section of the decoder.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20 10:35:50 +00:00
..
arm-semi.c
cpu64.c target-arm: Switch ARMCPUInfo arrays to use terminator entries 2014-01-14 10:09:04 +10:00
cpu-qom.h
cpu.c ARM: Convert MIDR to a property 2014-01-31 14:47:32 +00:00
cpu.h target-arm: Move arm_rmode_to_sf to a shared location. 2014-01-31 14:47:33 +00:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target-arm: A64: Implement SIMD FP compare and set insns 2014-02-20 10:35:49 +00:00
helper-a64.h target-arm: A64: Implement SIMD FP compare and set insns 2014-02-20 10:35:49 +00:00
helper.c exec: Make stl_*_phys input an AddressSpace 2014-02-11 22:57:18 +10:00
helper.h target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT 2014-02-08 14:47:28 +00:00
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h target-arm: Update generic cpreg code for AArch64 2014-01-04 22:15:44 +00:00
kvm-stub.c
kvm.c
machine.c target-arm: Widen exclusive-access support struct fields to 64 bits 2014-01-08 19:07:20 +00:00
Makefile.objs
neon_helper.c target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT 2014-02-08 14:47:28 +00:00
op_addsub.h
op_helper.c
translate-a64.c target-arm: A64: Implement floating point pairwise insns 2014-02-20 10:35:50 +00:00
translate.c target-arm: Add support for AArch32 64bit VCVTB and VCVTT 2014-02-08 14:47:28 +00:00
translate.h target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder 2014-01-07 19:17:58 +00:00