qemu-e2k/target/arm
Peter Maydell a5b1e1ab66 target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen
In gen_store_exclusive(), if the host does not have a cmpxchg128
primitive then we generate bad code for STXP for storing two 64-bit
values.  We generate a call to the exit_atomic helper, which never
returns, and set is_jmp to DISAS_NORETURN.  However, this is
forgetting that we have already emitted a brcond that jumps over this
call for the case where we don't hold the exclusive.  The effect is
that we don't generate any code to end the TB for the
exclusive-not-held execution path, which falls into the "exit with
TB_EXIT_REQUESTED" code that gen_tb_end() emits.  This then causes an
assert at runtime when cpu_loop_exec_tb() sees an EXIT_REQUESTED TB
return that wasn't for an interrupt or icount.

In particular, you can hit this case when using the clang sanitizers
and trying to run the xlnx-versal-virt acceptance test in 'make
check-acceptance'.  This bug was masked until commit 848126d11e
("meson: move int128 checks from configure") because we used to set
CONFIG_CMPXCHG128=1 and avoid the buggy codepath, but after that we
do not.

Fix the bug by not setting is_jmp.  The code after the exit_atomic
call up to the fail_label is dead, but TCG is smart enough to
eliminate it.  We do need to set 'tmp' to some valid value, though
(in the same way the exit_atomic-using code in tcg/tcg-op.c does).

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/953
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220331150858.96348-1-peter.maydell@linaro.org
2022-04-01 15:35:49 +01:00
..
hvf target/arm: Support PSCI 1.1 and SMCCC 1.0 2022-03-02 19:27:36 +00:00
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h accel/tcg: Add DisasContextBase argument to translator_ld* 2021-09-14 12:00:20 -07:00
arm-powerctl.c
arm-powerctl.h
cpu64.c target/arm: Provide cpu property for controling FEAT_LPA2 2022-03-07 14:32:21 +00:00
cpu_tcg.c target/arm: Implement arm_cpu_record_sigbus 2021-11-02 07:00:52 -04:00
cpu-param.h target/arm: Implement FEAT_LPA 2022-03-02 19:27:37 +00:00
cpu-qom.h target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro 2022-03-06 22:23:09 +01:00
cpu.c target/arm: Make rvbar settable after realize 2022-03-18 11:19:19 +00:00
cpu.h target/arm: Make rvbar settable after realize 2022-03-18 11:19:19 +00:00
crypto_helper.c
debug_helper.c target/arm: Suppress bp for exceptions with more priority 2021-12-15 10:35:26 +00:00
gdbstub64.c target/arm: Move gdbstub related code out of helper.c 2021-09-30 13:42:10 +01:00
gdbstub.c target/arm: Assert thumb pc is aligned 2021-12-15 10:35:26 +00:00
helper-a64.c arm: force flag recalculation when messing with DAIF 2022-02-08 10:56:28 +00:00
helper-a64.h
helper-mve.h target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
helper-sve.h
helper.c target/arm: Determine final stage 2 output PA space based on original IPA 2022-04-01 15:35:49 +01:00
helper.h target/arm: Take an exception if PC is misaligned 2021-12-15 10:35:26 +00:00
hvf_arm.h target: Use forward declared type instead of structure type 2022-03-06 22:22:40 +01:00
idau.h
internals.h target/arm: Fix MTE access checks for disabled SEL2 2022-04-01 15:35:48 +01:00
iwmmxt_helper.c
Kconfig
kvm64.c target/arm: Report KVM's actual PSCI version to guest in dtb 2022-03-02 19:27:37 +00:00
kvm_arm.h hvf: arm: Implement -cpu host 2021-09-21 16:28:26 +01:00
kvm-consts.h target/arm: Report KVM's actual PSCI version to guest in dtb 2022-03-02 19:27:37 +00:00
kvm-stub.c
kvm.c memory: Name all the memory listeners 2021-09-30 15:30:24 +02:00
m_helper.c target/arm: Log fault address for M-profile faults 2022-03-18 11:08:59 +00:00
m-nocp.decode
machine.c target/arm: Assert thumb pc is aligned 2021-12-15 10:35:26 +00:00
meson.build arm: Add Hypervisor.framework build target 2021-09-21 16:28:26 +01:00
monitor.c
mte_helper.c exec/exec-all: Move 'qemu/log.h' include in units requiring it 2022-02-21 10:18:06 +01:00
mve_helper.c target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
mve.decode target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_addsub.h
op_helper.c target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
pauth_helper.c target/arm: Fix pauth_check_trap vs SEL2 2022-03-18 10:55:15 +00:00
psci.c target/arm: Support PSCI 1.1 and SMCCC 1.0 2022-03-02 19:27:36 +00:00
sve_helper.c target/arm: Fix sve_ld1_z and sve_st1_z vs MMIO 2022-03-25 14:41:06 +00:00
sve.decode target/arm: Fix sve2 ldnt1 and stnt1 2022-03-18 10:55:15 +00:00
syndrome.h target/arm: Take an exception if PC is misaligned 2021-12-15 10:35:26 +00:00
t16.decode
t32.decode
tlb_helper.c target/arm: Take an exception if PC is misaligned 2021-12-15 10:35:26 +00:00
trace-events
trace.h
translate-a32.h exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate-a64.c target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen 2022-04-01 15:35:49 +01:00
translate-a64.h
translate-m-nocp.c target/arm: Add TB flag for "MVE insns not predicated" 2021-09-21 16:28:27 +01:00
translate-mve.c target/arm: Optimize MVE 1op-immediate insns 2021-09-21 16:28:27 +01:00
translate-neon.c target/arm/translate-neon: Simplify align field check for VLD3 2022-03-07 13:16:49 +00:00
translate-sve.c target/arm: Fix sve2 ldnt1 and stnt1 2022-03-18 10:55:15 +00:00
translate-vfp.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate.h target/arm: Add TB flag for "MVE insns not predicated" 2021-09-21 16:28:27 +01:00
vec_helper.c
vec_internal.h
vfp_helper.c
vfp-uncond.decode
vfp.decode