Richard Henderson bf754c96b2 target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields ... Use FIELD_DP32 instead of manual shifting and masking. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-26-richard.henderson@linaro.org>		2022-04-26 08:16:41 -07:00
..
alpha	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
arm	target/arm: Use tcg_constant_i32 in translate.h	2022-04-22 14:44:55 +01:00
avr	exec/translator: Pass the locked filepointer to disas_log hook	2022-04-20 10:51:11 -07:00
cris	exec/translator: Pass the locked filepointer to disas_log hook	2022-04-20 10:51:11 -07:00
hexagon	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
hppa	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
i386	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
m68k	exec/translator: Pass the locked filepointer to disas_log hook	2022-04-20 10:51:11 -07:00
microblaze	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
mips	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
nios2	target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields	2022-04-26 08:16:41 -07:00
openrisc	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
ppc	Misc cleanups	2022-04-21 09:27:54 -07:00
riscv	target/riscv: cpu: Enable native debug feature	2022-04-22 10:35:16 +10:00
rx	Fix usp/isp swapping upon clrpsw/setpsw.	2022-04-21 16:45:41 -07:00
s390x	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
sh4	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
sparc	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
tricore	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
xtensa	compiler.h: replace QEMU_NORETURN with G_NORETURN	2022-04-21 17:03:51 +04:00
Kconfig
meson.build