Fredrik Noring c42171c3bf target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1 ... DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic gen_muldiv. Signed-off-by: Fredrik Noring <noring@nocrew.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>		2018-11-17 19:29:34 +01:00
..
cp0_timer.c
cpu-qom.h
cpu.c	target/mips: Add disassembler support for nanoMIPS	2018-10-25 22:13:33 +02:00
cpu.h	target/mips: Introduce MXU registers	2018-10-29 14:13:47 +01:00
dsp_helper.c
gdbstub.c
helper.c	target/mips: Implement hardware page table walker for MIPS32	2018-10-18 20:37:20 +02:00
helper.h	target/mips: Add CP0 PWCtl register	2018-10-18 20:37:20 +02:00
internal.h	target/mips: Implement hardware page table walker for MIPS32	2018-10-18 20:37:20 +02:00
kvm_mips.h
kvm.c
lmi_helper.c
machine.c	target/mips: Add CP0 PWCtl register	2018-10-18 20:37:20 +02:00
Makefile.objs
mips-defs.h	target/mips: Define a bit for MXU in insn_flags	2018-10-29 14:13:47 +01:00
mips-semi.c
msa_helper.c
op_helper.c	target/mips: Implement hardware page table walker for MIPS32	2018-10-18 20:37:20 +02:00
TODO
trace-events
translate_init.inc.c	target/mips: Define the R5900 CPU	2018-10-24 15:20:31 +02:00
translate.c	target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1	2018-11-17 19:29:34 +01:00