8a14d31b00
When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) which are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also stored in host endian order to match the VMX registers. This ensures that TCG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
228 lines
8.0 KiB
C
228 lines
8.0 KiB
C
/*
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* PowerPC interal definitions for qemu.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_INTERNAL_H
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#define PPC_INTERNAL_H
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#define FUNC_MASK(name, ret_type, size, max_val) \
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static inline ret_type name(uint##size##_t start, \
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uint##size##_t end) \
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{ \
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ret_type ret, max_bit = size - 1; \
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\
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if (likely(start == 0)) { \
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ret = max_val << (max_bit - end); \
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} else if (likely(end == max_bit)) { \
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ret = max_val >> start; \
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} else { \
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ret = (((uint##size##_t)(-1ULL)) >> (start)) ^ \
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(((uint##size##_t)(-1ULL) >> (end)) >> 1); \
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if (unlikely(start > end)) { \
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return ~ret; \
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} \
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} \
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\
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return ret; \
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}
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#if defined(TARGET_PPC64)
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FUNC_MASK(MASK, target_ulong, 64, UINT64_MAX);
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#else
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FUNC_MASK(MASK, target_ulong, 32, UINT32_MAX);
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#endif
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FUNC_MASK(mask_u32, uint32_t, 32, UINT32_MAX);
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FUNC_MASK(mask_u64, uint64_t, 64, UINT64_MAX);
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/*****************************************************************************/
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/*** Instruction decoding ***/
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#define EXTRACT_HELPER(name, shift, nb) \
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static inline uint32_t name(uint32_t opcode) \
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{ \
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return extract32(opcode, shift, nb); \
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}
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#define EXTRACT_SHELPER(name, shift, nb) \
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static inline int32_t name(uint32_t opcode) \
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{ \
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return sextract32(opcode, shift, nb); \
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}
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#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
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static inline uint32_t name(uint32_t opcode) \
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{ \
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return extract32(opcode, shift1, nb1) << nb2 | \
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extract32(opcode, shift2, nb2); \
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}
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#define EXTRACT_HELPER_SPLIT_3(name, \
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d0_bits, shift_op_d0, shift_d0, \
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d1_bits, shift_op_d1, shift_d1, \
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d2_bits, shift_op_d2, shift_d2) \
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static inline int16_t name(uint32_t opcode) \
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{ \
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return \
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(((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
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(((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
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(((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
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}
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/* Opcode part 1 */
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EXTRACT_HELPER(opc1, 26, 6);
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/* Opcode part 2 */
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EXTRACT_HELPER(opc2, 1, 5);
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/* Opcode part 3 */
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EXTRACT_HELPER(opc3, 6, 5);
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/* Opcode part 4 */
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EXTRACT_HELPER(opc4, 16, 5);
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/* Update Cr0 flags */
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EXTRACT_HELPER(Rc, 0, 1);
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/* Update Cr6 flags (Altivec) */
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EXTRACT_HELPER(Rc21, 10, 1);
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/* Destination */
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EXTRACT_HELPER(rD, 21, 5);
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/* Source */
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EXTRACT_HELPER(rS, 21, 5);
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/* First operand */
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EXTRACT_HELPER(rA, 16, 5);
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/* Second operand */
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EXTRACT_HELPER(rB, 11, 5);
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/* Third operand */
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EXTRACT_HELPER(rC, 6, 5);
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/*** Get CRn ***/
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EXTRACT_HELPER(crfD, 23, 3);
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EXTRACT_HELPER(BF, 23, 3);
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EXTRACT_HELPER(crfS, 18, 3);
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EXTRACT_HELPER(crbD, 21, 5);
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EXTRACT_HELPER(crbA, 16, 5);
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EXTRACT_HELPER(crbB, 11, 5);
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/* SPR / TBL */
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EXTRACT_HELPER(_SPR, 11, 10);
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static inline uint32_t SPR(uint32_t opcode)
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{
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uint32_t sprn = _SPR(opcode);
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return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
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}
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/*** Get constants ***/
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/* 16 bits signed immediate value */
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EXTRACT_SHELPER(SIMM, 0, 16);
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/* 16 bits unsigned immediate value */
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EXTRACT_HELPER(UIMM, 0, 16);
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/* 5 bits signed immediate value */
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EXTRACT_SHELPER(SIMM5, 16, 5);
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/* 5 bits signed immediate value */
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EXTRACT_HELPER(UIMM5, 16, 5);
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/* 4 bits unsigned immediate value */
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EXTRACT_HELPER(UIMM4, 16, 4);
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/* Bit count */
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EXTRACT_HELPER(NB, 11, 5);
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/* Shift count */
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EXTRACT_HELPER(SH, 11, 5);
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/* lwat/stwat/ldat/lwat */
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EXTRACT_HELPER(FC, 11, 5);
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/* Vector shift count */
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EXTRACT_HELPER(VSH, 6, 4);
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/* Mask start */
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EXTRACT_HELPER(MB, 6, 5);
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/* Mask end */
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EXTRACT_HELPER(ME, 1, 5);
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/* Trap operand */
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EXTRACT_HELPER(TO, 21, 5);
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EXTRACT_HELPER(CRM, 12, 8);
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#ifndef CONFIG_USER_ONLY
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EXTRACT_HELPER(SR, 16, 4);
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#endif
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/* mtfsf/mtfsfi */
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EXTRACT_HELPER(FPBF, 23, 3);
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EXTRACT_HELPER(FPIMM, 12, 4);
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EXTRACT_HELPER(FPL, 25, 1);
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EXTRACT_HELPER(FPFLM, 17, 8);
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EXTRACT_HELPER(FPW, 16, 1);
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/* addpcis */
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EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
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#if defined(TARGET_PPC64)
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/* darn */
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EXTRACT_HELPER(L, 16, 2);
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#endif
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/*** Jump target decoding ***/
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/* Immediate address */
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static inline target_ulong LI(uint32_t opcode)
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{
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return (opcode >> 0) & 0x03FFFFFC;
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}
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static inline uint32_t BD(uint32_t opcode)
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{
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return (opcode >> 0) & 0xFFFC;
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}
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EXTRACT_HELPER(BO, 21, 5);
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EXTRACT_HELPER(BI, 16, 5);
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/* Absolute/relative address */
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EXTRACT_HELPER(AA, 1, 1);
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/* Link */
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EXTRACT_HELPER(LK, 0, 1);
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/* DFP Z22-form */
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EXTRACT_HELPER(DCM, 10, 6)
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/* DFP Z23-form */
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EXTRACT_HELPER(RMC, 9, 2)
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EXTRACT_HELPER(Rrm, 16, 1)
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EXTRACT_HELPER_SPLIT(DQxT, 3, 1, 21, 5);
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EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
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EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
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EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
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EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
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EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
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EXTRACT_HELPER(DM, 8, 2);
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EXTRACT_HELPER(UIM, 16, 2);
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EXTRACT_HELPER(SHW, 8, 2);
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EXTRACT_HELPER(SP, 19, 2);
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EXTRACT_HELPER(IMM8, 11, 8);
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EXTRACT_HELPER(DCMX, 16, 7);
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EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
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static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
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{
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vsr->VsrD(0) = env->vsr[n].VsrD(0);
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vsr->VsrD(1) = env->vsr[n].VsrD(1);
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}
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static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
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{
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env->vsr[n].VsrD(0) = vsr->VsrD(0);
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env->vsr[n].VsrD(1) = vsr->VsrD(1);
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}
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void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
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void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
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void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
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/* Raise a data fault alignment exception for the specified virtual address */
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void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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#endif /* PPC_INTERNAL_H */
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