Wilfred Mallawa 28ca4689ae hw: timer: ibex_timer: Fixup reading w/o register ... This change fixes a bug where a write only register is read. As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table the 'INTR_TEST0' register is write only. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-21 15:52:56 +10:00
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a9gtimer.h
allwinner-a10-pit.h
arm_mptimer.h
armv7m_systick.h	arm: Remove system_clock_scale global	2021-09-01 11:08:21 +01:00
aspeed_timer.h
avr_timer16.h	hw: Remove superfluous includes of hw/hw.h	2021-05-02 17:24:50 +02:00
bcm2835_systmr.h
cmsdk-apb-dualtimer.h
cmsdk-apb-timer.h
digic-timer.h
hpet.h
i8254_internal.h
i8254.h
ibex_timer.h	hw: timer: ibex_timer: Fixup reading w/o register	2022-01-21 15:52:56 +10:00
imx_epit.h
imx_gpt.h
mips_gictimer.h
mss-timer.h
npcm7xx_timer.h
nrf51_timer.h
renesas_cmt.h
renesas_tmr.h
sifive_pwm.h	hw/timer: Add SiFive PWM support	2021-09-21 07:56:49 +10:00
sse-counter.h	hw/timer/sse-counter: Model the SSE Subsystem System Counter	2021-03-08 17:20:01 +00:00
sse-timer.h	hw/timer/sse-timer: Model the SSE Subsystem System Timer	2021-03-08 17:20:01 +00:00
stellaris-gptm.h	hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale	2021-09-01 11:08:20 +01:00
stm32f2xx_timer.h
tmu012.h