qemu-e2k/hw/riscv
Yong-Xuan Wang ca334e10dc hw/riscv/virt.c: fix the interrupts-extended property format of PLIC
The interrupts-extended property of PLIC only has 2 * hart number
fields when KVM enabled, copy 4 * hart number fields to fdt will
expose some uninitialized value.

In this patch, I also refactor the code about the setting of
interrupts-extended property of PLIC for improved readability.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231218090543.22353-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10 18:47:47 +10:00
..
boot.c target/riscv: rename ext_icsr to ext_zicsr 2023-11-07 11:02:17 +10:00
Kconfig hw/riscv/virt-acpi-build.c: Add IO controllers and devices 2024-01-10 18:47:47 +10:00
meson.build hw/riscv/virt: Enable basic ACPI infrastructure 2023-03-06 11:35:04 -08:00
microchip_pfsoc.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
numa.c hw/riscv: Fix typo field in error_report 2023-07-19 14:31:41 +10:00
opentitan.c hw/riscv: opentitan: Fixup local variables shadowing 2023-09-29 10:07:20 +02:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv/shakti_c: Check CPU type in machine_run_board_init() 2024-01-05 16:20:15 +01:00
sifive_e.c riscv: Fix SiFive E CLINT clock frequency 2023-11-22 13:57:19 +10:00
sifive_u.c hw/sd: Introduce a "sd-card" SPI variant model 2023-09-01 11:40:04 +02:00
spike.c hw/riscv: Validate cluster and NUMA node boundary 2023-06-26 10:23:01 +02:00
virt-acpi-build.c hw/riscv/virt-acpi-build.c: Add PLIC in MADT 2024-01-10 18:47:47 +10:00
virt.c hw/riscv/virt.c: fix the interrupts-extended property format of PLIC 2024-01-10 18:47:47 +10:00