qemu-e2k/target
Peter Maydell cb4a0a3444 target/arm: Store TCR_EL* registers as uint64_t
Change the representation of the TCR_EL* registers in the CPU state
struct from struct TCR to uint64_t.  This allows us to drop the
custom vmsa_ttbcr_raw_write() function, moving the "enforce RES0"
checks to their more usual location in the writefn
vmsa_ttbcr_write().  We also don't need the resetfn any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220714132303.1287193-7-peter.maydell@linaro.org
2022-07-18 13:20:13 +01:00
..
alpha
arm target/arm: Store TCR_EL* registers as uint64_t 2022-07-18 13:20:13 +01:00
avr target/avr: Drop avr_cpu_memory_rw_debug() 2022-06-20 13:11:36 -07:00
cris
hexagon
hppa
i386 hvf: Enable RDTSCP support 2022-07-13 00:05:39 +02:00
loongarch target/loongarch: Clean up tlb when cpu reset 2022-07-05 16:17:53 +05:30
m68k target/m68k: Make semihosting system only 2022-06-28 10:13:22 +05:30
microblaze
mips target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRING 2022-07-12 22:32:22 +02:00
nios2 target/nios2: Move nios2-semi.c to nios2_softmmu_ss 2022-06-28 10:18:57 +05:30
openrisc
ppc target/ppc: Fix MPC8555 and MPC8560 core type to e500v1 2022-07-06 10:30:01 -03:00
riscv target/riscv: Update default priority table for local interrupts 2022-07-03 10:03:20 +10:00
rx
s390x target/s390x: Exit tb after executing ex_value 2022-07-06 19:04:57 +02:00
sh4
sparc
tricore
xtensa
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00