qemu-e2k/include/hw/i386
Prasad Singamsetty 37f51384ae intel-iommu: Extend address width to 48 bits
The current implementation of Intel IOMMU code only supports 39 bits
iova address width. This patch provides a new parameter (x-aw-bits)
for intel-iommu to extend its address width to 48 bits but keeping the
default the same (39 bits). The reason for not changing the default
is to avoid potential compatibility problems with live migration of
intel-iommu enabled QEMU guest. The only valid values for 'x-aw-bits'
parameter are 39 and 48.

After enabling larger address width (48), we should be able to map
larger iova addresses in the guest. For example, a QEMU guest that
is configured with large memory ( >=1TB ). To check whether 48 bits
aw is enabled, we can grep in the guest dmesg output with line:
"DMAR: Host address width 48".

Signed-off-by: Prasad Singamsetty <prasad.singamsety@oracle.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-01-18 21:52:38 +02:00
..
apic_internal.h
apic-msidef.h i386/msi: Correct mask of destination ID in MSI address 2017-12-01 18:28:15 +02:00
apic.h apic: add function to apic that will be used by hvf 2017-12-22 15:01:19 +01:00
ich9.h
intel_iommu.h intel-iommu: Extend address width to 48 bits 2018-01-18 21:52:38 +02:00
ioapic_internal.h
ioapic.h
pc.h target/i386: add clflushopt to "Skylake-Server" cpu model 2018-01-17 23:04:31 -02:00
topology.h
x86-iommu.h intel_iommu: remove X86_IOMMU_PCI_DEVFN_MAX 2017-12-22 01:42:03 +02:00