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qemu-e2k/target/riscv
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Peter Maydell 68d8ef4ec5 TCG Plugins initial implementation 
- use --enable-plugins @ configure
   - low impact introspection (-plugin empty.so to measure overhead)
   - plugins cannot alter guest state
   - example plugins included in source tree (tests/plugins)
   - -d plugin to enable plugin output in logs
   - check-tcg runs extra tests when plugins enabled
   - documentation in docs/devel/plugins.rst
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Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-plugins-281019-4' into staging

TCG Plugins initial implementation

  - use --enable-plugins @ configure
  - low impact introspection (-plugin empty.so to measure overhead)
  - plugins cannot alter guest state
  - example plugins included in source tree (tests/plugins)
  - -d plugin to enable plugin output in logs
  - check-tcg runs extra tests when plugins enabled
  - documentation in docs/devel/plugins.rst

# gpg: Signature made Mon 28 Oct 2019 15:13:23 GMT
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-tcg-plugins-281019-4: (57 commits)
  travis.yml: enable linux-gcc-debug-tcg cache
  MAINTAINERS: add me for the TCG plugins code
  scripts/checkpatch.pl: don't complain about (foo, /* empty */)
  .travis.yml: add --enable-plugins tests
  include/exec: wrap cpu_ldst.h in CONFIG_TCG
  accel/stubs: reduce headers from tcg-stub
  tests/plugin: add hotpages to analyse memory access patterns
  tests/plugin: add instruction execution breakdown
  tests/plugin: add a hotblocks plugin
  tests/tcg: enable plugin testing
  tests/tcg: drop test-i386-fprem from TESTS when not SLOW
  tests/tcg: move "virtual" tests to EXTRA_TESTS
  tests/tcg: set QEMU_OPTS for all cris runs
  tests/tcg/Makefile.target: fix path to config-host.mak
  tests/plugin: add sample plugins
  linux-user: support -plugin option
  vl: support -plugin option
  plugin: add qemu_plugin_outs helper
  plugin: add qemu_plugin_insn_disas helper
  plugin: expand the plugin_init function to include an info block
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 		2019-10-30 14:10:32 +00:00
..
insn_trans tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
Makefile.objs riscv: hmp: Add a command to show virtual memory mappings 2019-09-17 08:42:43 -07:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu.c RISC-V: Implement cpu_do_transaction_failed 2019-10-28 07:47:27 -07:00
cpu.h RISC-V: Implement cpu_do_transaction_failed 2019-10-28 07:47:27 -07:00
cpu_bits.h target/riscv: Update the Hypervisor CSRs to v0.4 2019-09-17 08:42:43 -07:00
cpu_helper.c linux-user/riscv: Propagate fault address 2019-10-28 07:47:27 -07:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
csr.c riscv: Skip checking CSR privilege level in debugger mode 2019-10-28 07:46:53 -07:00
fpu_helper.c target/riscv: rationalise softfloat includes 2019-08-19 12:07:13 +01:00
gdbstub.c target/riscv: Make the priv register writable by GDB 2019-10-28 07:47:29 -07:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-24 12:09:22 -07:00
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
insn32.decode target/riscv: Name the argument sets for all of insn32 formats 2019-05-24 12:09:22 -07:00
instmap.h Supply missing header guards 2019-06-12 13:20:21 +02:00
monitor.c riscv: hmp: Add a command to show virtual memory mappings 2019-09-17 08:42:43 -07:00
op_helper.c target/riscv: Use env_cpu, env_archcpu 2019-06-10 07:03:42 -07:00
pmp.c target/riscv: PMP violation due to wrong size parameter 2019-10-28 08:46:33 -07:00
pmp.h RISC-V: Check for the effective memory privilege mode during PMP checks 2019-06-23 23:44:41 -07:00
trace-events target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events 2019-09-17 08:42:42 -07:00
translate.c target/riscv: fetch code with translator_ld 2019-10-28 15:12:38 +00:00