9b945a9ee3
The timer controller can be driven by either an external 1MHz clock or by the APB clock. Today, the model makes the assumption that the APB frequency is always set to 24MHz but this is incorrect. The AST2400 SoC on the palmetto machines uses a 48MHz input clock source and the APB can be set to 48MHz. The consequence is a general system slowdown. The QEMU machines using the AST2500 SoC do not seem impacted today because the APB frequency is still set to 24MHz. We fix the timer frequency for all SoCs by linking the Timer model to the SCU model. The APB frequency driving the timers is now the one configured for the SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180622075700.5923-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
/*
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* ASPEED AST2400 Timer
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef ASPEED_TIMER_H
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#define ASPEED_TIMER_H
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#include "qemu/timer.h"
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typedef struct AspeedSCUState AspeedSCUState;
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#define ASPEED_TIMER(obj) \
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OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
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#define TYPE_ASPEED_TIMER "aspeed.timer"
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#define ASPEED_TIMER_NR_TIMERS 8
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typedef struct AspeedTimer {
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qemu_irq irq;
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uint8_t id;
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QEMUTimer timer;
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/**
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* Track the line level as the ASPEED timers implement edge triggered
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* interrupts, signalling with both the rising and falling edge.
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*/
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int32_t level;
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uint32_t reload;
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uint32_t match[2];
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uint64_t start;
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} AspeedTimer;
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typedef struct AspeedTimerCtrlState {
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/*< private >*/
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SysBusDevice parent;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t ctrl;
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uint32_t ctrl2;
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AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
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AspeedSCUState *scu;
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} AspeedTimerCtrlState;
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#endif /* ASPEED_TIMER_H */
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