9b945a9ee3
The timer controller can be driven by either an external 1MHz clock or by the APB clock. Today, the model makes the assumption that the APB frequency is always set to 24MHz but this is incorrect. The AST2400 SoC on the palmetto machines uses a 48MHz input clock source and the APB can be set to 48MHz. The consequence is a general system slowdown. The QEMU machines using the AST2500 SoC do not seem impacted today because the APB frequency is still set to 24MHz. We fix the timer frequency for all SoCs by linking the Timer model to the SCU model. The APB frequency driving the timers is now the one configured for the SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180622075700.5923-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| a9gtimer.h | ||
| allwinner-a10-pit.h | ||
| arm_mptimer.h | ||
| armv7m_systick.h | ||
| aspeed_timer.h | ||
| cmsdk-apb-timer.h | ||
| digic-timer.h | ||
| hpet.h | ||
| i8254_internal.h | ||
| i8254.h | ||
| imx_epit.h | ||
| imx_gpt.h | ||
| m48t59.h | ||
| mc146818rtc_regs.h | ||
| mc146818rtc.h | ||
| mips_gictimer.h | ||
| mss-timer.h | ||
| stm32f2xx_timer.h | ||
| sun4v-rtc.h | ||
| xlnx-zynqmp-rtc.h | ||