qemu-e2k/target/i386/tcg
Paolo Bonzini d1c1a4222c target/i386: reimplement 0x0f 0x78-0x7f, add AVX
These are a mixed batch, including the first two horizontal
(66 and F2 only) operations, more moves, and SSE4a extract/insert.

Because SSE4a is pretty rare, I chose to leave the helper as they are,
but it is possible to unify them by loading index and length from the
source XMM register and generating deposit or extract TCG ops.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-18 13:58:05 +02:00
..
sysemu target/i386: Use probe_access_full for final stage2 translation 2022-10-18 13:58:04 +02:00
user target/i386: Raise #GP on unaligned m128 accesses when required. 2022-09-18 09:17:40 +02:00
bpt_helper.c
cc_helper_template.h
cc_helper.c
decode-new.c.inc target/i386: reimplement 0x0f 0x78-0x7f, add AVX 2022-10-18 13:58:05 +02:00
decode-new.h target/i386: validate SSE prefixes directly in the decoding table 2022-10-18 13:58:04 +02:00
emit.c.inc target/i386: reimplement 0x0f 0x78-0x7f, add AVX 2022-10-18 13:58:05 +02:00
excp_helper.c target/i386: Raise #GP on unaligned m128 accesses when required. 2022-09-18 09:17:40 +02:00
fpu_helper.c target/i386: Introduce 256-bit vector helpers 2022-10-18 13:58:04 +02:00
helper-tcg.h target/i386: Raise #GP on unaligned m128 accesses when required. 2022-09-18 09:17:40 +02:00
int_helper.c
mem_helper.c
meson.build
misc_helper.c
mpx_helper.c
seg_helper.c target/i386: Truncate values for lcall_real to i32 2022-10-11 09:36:01 +02:00
seg_helper.h
tcg-cpu.c target/i386: Enable TARGET_TB_PCREL 2022-10-11 09:36:01 +02:00
tcg-cpu.h
tcg-stub.c
translate.c target/i386: reimplement 0x0f 0x78-0x7f, add AVX 2022-10-18 13:58:05 +02:00