a8170e5e97
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
118 lines
3.8 KiB
C
118 lines
3.8 KiB
C
#ifndef CPU_COMMON_H
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#define CPU_COMMON_H 1
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/* CPU interfaces that are target independent. */
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#include "hwaddr.h"
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#ifndef NEED_CPU_H
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#include "poison.h"
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#endif
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#include "bswap.h"
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#include "qemu-queue.h"
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#if !defined(CONFIG_USER_ONLY)
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enum device_endian {
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DEVICE_NATIVE_ENDIAN,
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DEVICE_BIG_ENDIAN,
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DEVICE_LITTLE_ENDIAN,
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};
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/* address in the RAM (different from a physical address) */
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#if defined(CONFIG_XEN_BACKEND)
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typedef uint64_t ram_addr_t;
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# define RAM_ADDR_MAX UINT64_MAX
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# define RAM_ADDR_FMT "%" PRIx64
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#else
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typedef uintptr_t ram_addr_t;
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# define RAM_ADDR_MAX UINTPTR_MAX
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# define RAM_ADDR_FMT "%" PRIxPTR
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#endif
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/* memory API */
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typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
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typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
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void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
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/* This should only be used for ram local to a device. */
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void *qemu_get_ram_ptr(ram_addr_t addr);
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void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size);
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/* Same but slower, to use for migration, where the order of
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* RAMBlocks must not change. */
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void *qemu_safe_ram_ptr(ram_addr_t addr);
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void qemu_put_ram_ptr(void *addr);
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/* This should not be used by devices. */
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int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
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ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
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void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
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void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
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int len, int is_write);
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static inline void cpu_physical_memory_read(hwaddr addr,
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void *buf, int len)
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{
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cpu_physical_memory_rw(addr, buf, len, 0);
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}
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static inline void cpu_physical_memory_write(hwaddr addr,
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const void *buf, int len)
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{
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cpu_physical_memory_rw(addr, (void *)buf, len, 1);
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}
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void *cpu_physical_memory_map(hwaddr addr,
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hwaddr *plen,
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int is_write);
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void cpu_physical_memory_unmap(void *buffer, hwaddr len,
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int is_write, hwaddr access_len);
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void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
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void cpu_unregister_map_client(void *cookie);
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bool cpu_physical_memory_is_io(hwaddr phys_addr);
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/* Coalesced MMIO regions are areas where write operations can be reordered.
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* This usually implies that write operations are side-effect free. This allows
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* batching which can make a major impact on performance when using
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* virtualization.
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*/
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void qemu_flush_coalesced_mmio_buffer(void);
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uint32_t ldub_phys(hwaddr addr);
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uint32_t lduw_le_phys(hwaddr addr);
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uint32_t lduw_be_phys(hwaddr addr);
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uint32_t ldl_le_phys(hwaddr addr);
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uint32_t ldl_be_phys(hwaddr addr);
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uint64_t ldq_le_phys(hwaddr addr);
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uint64_t ldq_be_phys(hwaddr addr);
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void stb_phys(hwaddr addr, uint32_t val);
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void stw_le_phys(hwaddr addr, uint32_t val);
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void stw_be_phys(hwaddr addr, uint32_t val);
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void stl_le_phys(hwaddr addr, uint32_t val);
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void stl_be_phys(hwaddr addr, uint32_t val);
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void stq_le_phys(hwaddr addr, uint64_t val);
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void stq_be_phys(hwaddr addr, uint64_t val);
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#ifdef NEED_CPU_H
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uint32_t lduw_phys(hwaddr addr);
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uint32_t ldl_phys(hwaddr addr);
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uint64_t ldq_phys(hwaddr addr);
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void stl_phys_notdirty(hwaddr addr, uint32_t val);
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void stq_phys_notdirty(hwaddr addr, uint64_t val);
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void stw_phys(hwaddr addr, uint32_t val);
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void stl_phys(hwaddr addr, uint32_t val);
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void stq_phys(hwaddr addr, uint64_t val);
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#endif
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void cpu_physical_memory_write_rom(hwaddr addr,
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const uint8_t *buf, int len);
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extern struct MemoryRegion io_mem_ram;
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extern struct MemoryRegion io_mem_rom;
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extern struct MemoryRegion io_mem_unassigned;
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extern struct MemoryRegion io_mem_notdirty;
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#endif
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#endif /* !CPU_COMMON_H */
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