562 lines
15 KiB
C
562 lines
15 KiB
C
/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h"
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#include "pc.h"
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#include "apm.h"
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#include "pm_smbus.h"
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#include "pci.h"
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#include "acpi.h"
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#include "sysemu.h"
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#include "range.h"
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//#define DEBUG
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define PIIX4_DPRINTF(format, ...) do { } while (0)
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#endif
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#define ACPI_DBG_IO_ADDR 0xb044
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#define GPE_BASE 0xafe0
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#define GPE_LEN 4
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#define PCI_BASE 0xae00
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#define PCI_EJ_BASE 0xae08
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#define PCI_RMV_BASE 0xae0c
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#define PIIX4_PCI_HOTPLUG_STATUS 2
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struct pci_status {
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uint32_t up;
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uint32_t down;
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};
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typedef struct PIIX4PMState {
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PCIDevice dev;
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IORange ioport;
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ACPIPM1EVT pm1a;
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ACPIPM1CNT pm1_cnt;
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APMState apm;
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ACPIPMTimer tmr;
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PMSMBus smb;
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uint32_t smb_io_base;
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qemu_irq irq;
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qemu_irq smi_irq;
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int kvm_enabled;
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/* for pci hotplug */
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ACPIGPE gpe;
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struct pci_status pci0_status;
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uint32_t pci0_hotplug_enable;
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} PIIX4PMState;
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static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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static void pm_update_sci(PIIX4PMState *s)
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{
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
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sci_level = (((pmsts & s->pm1a.en) &
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(ACPI_BITMASK_RT_CLOCK_ENABLE |
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ACPI_BITMASK_POWER_BUTTON_ENABLE |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
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(((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
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qemu_set_irq(s->irq, sci_level);
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
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!(pmsts & ACPI_BITMASK_TIMER_STATUS));
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}
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static void pm_tmr_timer(ACPIPMTimer *tmr)
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{
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PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
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pm_update_sci(s);
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}
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static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
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uint64_t val)
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{
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PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
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if (width != 2) {
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PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
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(unsigned)addr, width, (unsigned)val);
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}
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switch(addr) {
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case 0x00:
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acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
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pm_update_sci(s);
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break;
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case 0x02:
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s->pm1a.en = val;
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pm_update_sci(s);
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break;
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case 0x04:
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acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
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break;
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default:
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break;
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}
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PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
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(unsigned int)val);
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}
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static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
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uint64_t *data)
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{
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PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
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uint32_t val;
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switch(addr) {
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case 0x00:
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val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
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break;
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case 0x02:
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val = s->pm1a.en;
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break;
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case 0x04:
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val = s->pm1_cnt.cnt;
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break;
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case 0x08:
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val = acpi_pm_tmr_get(&s->tmr);
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break;
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default:
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val = 0;
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break;
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}
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PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
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*data = val;
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}
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static const IORangeOps pm_iorange_ops = {
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.read = pm_ioport_read,
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.write = pm_ioport_write,
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};
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static void apm_ctrl_changed(uint32_t val, void *arg)
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{
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PIIX4PMState *s = arg;
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/* ACPI specs 3.0, 4.7.2.5 */
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acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
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if (s->dev.config[0x5b] & (1 << 1)) {
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if (s->smi_irq) {
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qemu_irq_raise(s->smi_irq);
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}
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}
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}
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
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}
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static void pm_io_space_update(PIIX4PMState *s)
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{
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uint32_t pm_io_base;
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if (s->dev.config[0x80] & 1) {
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
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ioport_register(&s->ioport);
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}
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}
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static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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pci_default_write_config(d, address, val, len);
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if (range_covers_byte(address, len, 0x80))
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pm_io_space_update((PIIX4PMState *)d);
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}
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static int vmstate_acpi_post_load(void *opaque, int version_id)
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{
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PIIX4PMState *s = opaque;
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pm_io_space_update(s);
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return 0;
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}
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#define VMSTATE_GPE_ARRAY(_field, _state) \
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{ \
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.name = (stringify(_field)), \
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.version_id = 0, \
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.num = GPE_LEN, \
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.info = &vmstate_info_uint16, \
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.size = sizeof(uint16_t), \
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.flags = VMS_ARRAY | VMS_POINTER, \
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.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
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}
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static const VMStateDescription vmstate_gpe = {
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.name = "gpe",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_GPE_ARRAY(sts, ACPIGPE),
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VMSTATE_GPE_ARRAY(en, ACPIGPE),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pci_status = {
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.name = "pci_status",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(up, struct pci_status),
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VMSTATE_UINT32(down, struct pci_status),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_acpi = {
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.name = "piix4_pm",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
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VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
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VMSTATE_UINT16(pm1a.en, PIIX4PMState),
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VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(tmr.timer, PIIX4PMState),
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VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
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VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
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VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
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struct pci_status),
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VMSTATE_END_OF_LIST()
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}
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};
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static void piix4_update_hotplug(PIIX4PMState *s)
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{
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PCIDevice *dev = &s->dev;
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BusState *bus = qdev_get_parent_bus(&dev->qdev);
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DeviceState *qdev, *next;
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s->pci0_hotplug_enable = ~0;
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QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
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PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
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PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
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int slot = PCI_SLOT(pdev->devfn);
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if (info->no_hotplug) {
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s->pci0_hotplug_enable &= ~(1 << slot);
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}
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}
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}
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static void piix4_reset(void *opaque)
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{
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PIIX4PMState *s = opaque;
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uint8_t *pci_conf = s->dev.config;
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pci_conf[0x58] = 0;
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pci_conf[0x59] = 0;
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pci_conf[0x5a] = 0;
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pci_conf[0x5b] = 0;
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if (s->kvm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02;
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}
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piix4_update_hotplug(s);
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}
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static void piix4_powerdown(void *opaque, int irq, int power_failing)
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{
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PIIX4PMState *s = opaque;
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ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
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ACPIPMTimer *tmr = s? &s->tmr: NULL;
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acpi_pm1_evt_power_down(pm1a, tmr);
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}
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static int piix4_pm_initfn(PCIDevice *dev)
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{
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PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
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uint8_t *pci_conf;
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pci_conf = s->dev.config;
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pci_conf[0x06] = 0x80;
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pci_conf[0x07] = 0x02;
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pci_conf[0x09] = 0x00;
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pci_conf[0x3d] = 0x01; // interrupt pin 1
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pci_conf[0x40] = 0x01; /* PM io base read only bit */
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/* APM */
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apm_init(&s->apm, apm_ctrl_changed, s);
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register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
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if (s->kvm_enabled) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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* support SMM mode. */
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pci_conf[0x5B] = 0x02;
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}
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/* XXX: which specification is used ? The i82731AB has different
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mappings */
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pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
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pci_conf[0x63] = 0x60;
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pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
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(serial_hds[1] != NULL ? 0x90 : 0);
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pci_conf[0x90] = s->smb_io_base | 1;
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pci_conf[0x91] = s->smb_io_base >> 8;
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pci_conf[0xd2] = 0x09;
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register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
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register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
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acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
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acpi_gpe_init(&s->gpe, GPE_LEN);
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qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
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pm_smbus_init(&s->dev.qdev, &s->smb);
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qemu_register_reset(piix4_reset, s);
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piix4_acpi_system_hot_add_init(dev->bus, s);
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return 0;
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}
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
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int kvm_enabled)
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{
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PCIDevice *dev;
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PIIX4PMState *s;
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dev = pci_create(bus, devfn, "PIIX4_PM");
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qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
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s = DO_UPCAST(PIIX4PMState, dev, dev);
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s->irq = sci_irq;
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acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
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s->smi_irq = smi_irq;
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s->kvm_enabled = kvm_enabled;
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qdev_init_nofail(&dev->qdev);
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return s->smb.smbus;
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}
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static PCIDeviceInfo piix4_pm_info = {
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.qdev.name = "PIIX4_PM",
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.qdev.desc = "PM",
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.qdev.size = sizeof(PIIX4PMState),
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.qdev.vmsd = &vmstate_acpi,
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.qdev.no_user = 1,
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.no_hotplug = 1,
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.init = piix4_pm_initfn,
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.config_write = pm_write_config,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = PCI_DEVICE_ID_INTEL_82371AB_3,
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.revision = 0x03,
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.class_id = PCI_CLASS_BRIDGE_OTHER,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void piix4_pm_register(void)
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{
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pci_qdev_register(&piix4_pm_info);
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}
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device_init(piix4_pm_register);
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static uint32_t gpe_readb(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val = acpi_gpe_ioport_readb(&s->gpe, addr);
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PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
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return val;
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}
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static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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acpi_gpe_ioport_writeb(&s->gpe, addr, val);
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pm_update_sci(s);
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PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
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}
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static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
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{
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uint32_t val = 0;
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struct pci_status *g = opaque;
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switch (addr) {
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case PCI_BASE:
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val = g->up;
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break;
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case PCI_BASE + 4:
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val = g->down;
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break;
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default:
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break;
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}
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PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
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return val;
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}
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static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
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{
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struct pci_status *g = opaque;
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switch (addr) {
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case PCI_BASE:
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g->up = val;
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break;
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case PCI_BASE + 4:
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g->down = val;
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break;
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}
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PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
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}
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static uint32_t pciej_read(void *opaque, uint32_t addr)
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{
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PIIX4_DPRINTF("pciej read %x\n", addr);
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return 0;
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}
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static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
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{
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BusState *bus = opaque;
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DeviceState *qdev, *next;
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PCIDevice *dev;
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PCIDeviceInfo *info;
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int slot = ffs(val) - 1;
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QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
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dev = DO_UPCAST(PCIDevice, qdev, qdev);
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info = container_of(qdev->info, PCIDeviceInfo, qdev);
|
|
if (PCI_SLOT(dev->devfn) == slot && !info->no_hotplug) {
|
|
qdev_free(qdev);
|
|
}
|
|
}
|
|
|
|
|
|
PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
|
|
}
|
|
|
|
static uint32_t pcirmv_read(void *opaque, uint32_t addr)
|
|
{
|
|
PIIX4PMState *s = opaque;
|
|
|
|
return s->pci0_hotplug_enable;
|
|
}
|
|
|
|
static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
return;
|
|
}
|
|
|
|
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
|
|
PCIHotplugState state);
|
|
|
|
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
|
|
{
|
|
struct pci_status *pci0_status = &s->pci0_status;
|
|
|
|
register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
|
|
register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s);
|
|
acpi_gpe_blk(&s->gpe, GPE_BASE);
|
|
|
|
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
|
|
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status);
|
|
|
|
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
|
|
register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus);
|
|
|
|
register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
|
|
register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
|
|
|
|
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
|
|
}
|
|
|
|
static void enable_device(PIIX4PMState *s, int slot)
|
|
{
|
|
s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
|
|
s->pci0_status.up |= (1 << slot);
|
|
}
|
|
|
|
static void disable_device(PIIX4PMState *s, int slot)
|
|
{
|
|
s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
|
|
s->pci0_status.down |= (1 << slot);
|
|
}
|
|
|
|
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
|
|
PCIHotplugState state)
|
|
{
|
|
int slot = PCI_SLOT(dev->devfn);
|
|
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
|
|
DO_UPCAST(PCIDevice, qdev, qdev));
|
|
|
|
/* Don't send event when device is enabled during qemu machine creation:
|
|
* it is present on boot, no hotplug event is necessary. We do send an
|
|
* event when the device is disabled later. */
|
|
if (state == PCI_COLDPLUG_ENABLED) {
|
|
return 0;
|
|
}
|
|
|
|
s->pci0_status.up = 0;
|
|
s->pci0_status.down = 0;
|
|
if (state == PCI_HOTPLUG_ENABLED) {
|
|
enable_device(s, slot);
|
|
} else {
|
|
disable_device(s, slot);
|
|
}
|
|
|
|
pm_update_sci(s);
|
|
|
|
return 0;
|
|
}
|