qemu-e2k/target/ppc
Daniel Henrique Barboza 1f26c75191 PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.

The following operations happens during an EBB:

- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).

The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].

This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.

[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:19 +01:00
..
translate PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
Kconfig
arch_dump.c
compat.c
cpu-models.c
cpu-models.h
cpu-param.h
cpu-qom.h
cpu.c
cpu.h PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
cpu_init.c target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event 2021-12-17 17:57:18 +01:00
dfp_helper.c
excp_helper.c PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
fpu_helper.c target/ppc: move xscvqpdp to decodetree 2021-12-17 17:57:18 +01:00
gdbstub.c
helper.h PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
helper_regs.c target/ppc: enable PMU instruction count 2021-12-17 17:57:18 +01:00
helper_regs.h
insn32.decode PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
insn64.decode
int_helper.c
internal.h
kvm-stub.c
kvm.c
kvm_ppc.h
machine.c
mem_helper.c
meson.build target/ppc: introduce PMUEventType and PMU overflow timers 2021-12-17 17:57:18 +01:00
mfrom_table.c.inc
mfrom_table_gen.c
misc_helper.c
mmu-book3s-v3.c
mmu-book3s-v3.h
mmu-books.h
mmu-hash32.c
mmu-hash32.h
mmu-hash64.c
mmu-hash64.h
mmu-radix64.c
mmu-radix64.h
mmu_common.c
mmu_helper.c
monitor.c
power8-pmu-regs.c.inc target/ppc: enable PMU instruction count 2021-12-17 17:57:18 +01:00
power8-pmu.c target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event 2021-12-17 17:57:18 +01:00
power8-pmu.h target/ppc: enable PMU instruction count 2021-12-17 17:57:18 +01:00
spr_tcg.h target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event 2021-12-17 17:57:18 +01:00
tcg-stub.c
timebase_helper.c
trace-events
trace.h
translate.c PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
user_only_helper.c