Daniel Henrique Barboza d57dfe4b37 trans_rvv.c.inc: remove redundant mark_vs_dirty() calls ... trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of their 'ifs'. conditionals. Call it just once in the end like other functions are doing. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240314175704.478276-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-03-22 15:23:08 +10:00
..
insn_trans	trans_rvv.c.inc: remove redundant mark_vs_dirty() calls	2024-03-22 15:23:08 +10:00
kvm	migration: export migration_is_running	2024-03-11 16:28:59 -04:00
tcg	target/riscv: do not enable all named features by default	2024-03-22 15:10:45 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: FCSR doesn't contain vxrm and vxsat	2024-02-09 20:43:14 +10:00
cpu_cfg.h	target/riscv: do not enable all named features by default	2024-03-22 15:10:45 +10:00
cpu_helper.c	target/riscv: Fix privilege mode of G-stage translation for debugging	2024-03-08 20:48:03 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target/riscv: add rv32i, rv32e and rv64e CPUs	2024-02-09 20:49:41 +10:00
cpu.c	target/riscv: do not enable all named features by default	2024-03-22 15:10:45 +10:00
cpu.h	target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit	2024-03-08 20:48:03 +10:00
crypto_helper.c
csr.c	target/riscv: UPDATE xATP write CSR	2024-03-08 16:38:09 +10:00
debug.c	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
debug.h
fpu_helper.c
gdbstub.c	gdbstub: Add members to identify registers to GDBFeature	2024-02-28 09:10:11 +00:00
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig	kconfig: use "select" to enable semihosting	2024-02-09 17:52:30 +00:00
m128_helper.c
machine.c	target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit	2024-03-08 20:48:03 +10:00
meson.build
monitor.c
op_helper.c	target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index	2024-02-03 16:46:10 +10:00
pmp.c
pmp.h
pmu.c
pmu.h	target/riscv: Add missing include guard in pmu.h	2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c	target: Improve error reporting for CpuModelInfo member @props	2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	RISC-V: Add support for Ztso	2024-03-08 19:47:48 +10:00
vcrypto_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_internals.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_internals.h	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c