Philipp Tomsich d7a4fcb034 target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci ... The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-10-07 08:41:33 +10:00
..
insn_trans	target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci	2021-10-07 08:41:33 +10:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
bitmanip_helper.c	target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci	2021-10-07 08:41:33 +10:00
cpu_bits.h	target/riscv: csr: Rename HCOUNTEREN_CY and friends	2021-09-21 12:10:47 +10:00
cpu_helper.c	target/riscv: Backup/restore mstatus.SD bit when virtual register swapped	2021-09-21 12:10:22 +10:00
cpu_user.h
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties	2021-10-07 08:32:55 +10:00
cpu.h	target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties	2021-10-07 08:32:55 +10:00
csr.c	target/riscv: csr: Rename HCOUNTEREN_CY and friends	2021-09-21 12:10:47 +10:00
fpu_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
gdbstub.c	target/riscv: gdbstub: Fix dynamic CSR XML generation	2021-06-24 05:00:12 -07:00
helper.h	target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci	2021-10-07 08:41:33 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci	2021-10-07 08:41:33 +10:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
machine.c	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
meson.build	target/riscv: rvb: generalized reverse	2021-06-08 09:59:45 +10:00
monitor.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
op_helper.c	target/riscv: Reorg csr instructions	2021-09-01 11:59:12 +10:00
pmp.c	target/riscv: pmp: Fix some typos	2021-07-15 08:56:00 +10:00
pmp.h	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	accel/tcg: Add DisasContextBase argument to translator_ld*	2021-09-14 12:00:20 -07:00
vector_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00