5aeb368966
The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org |
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| macio | ||
| a9scu.h | ||
| arm11scu.h | ||
| arm_integrator_debug.h | ||
| armsse-cpuid.h | ||
| aspeed_scu.h | ||
| aspeed_sdmc.h | ||
| auxbus.h | ||
| bcm2835_mbox_defs.h | ||
| bcm2835_mbox.h | ||
| bcm2835_property.h | ||
| bcm2835_rng.h | ||
| imx2_wdt.h | ||
| imx6_ccm.h | ||
| imx6_src.h | ||
| imx6ul_ccm.h | ||
| imx7_ccm.h | ||
| imx7_gpr.h | ||
| imx7_snvs.h | ||
| imx25_ccm.h | ||
| imx31_ccm.h | ||
| imx_ccm.h | ||
| iotkit-secctl.h | ||
| iotkit-sysctl.h | ||
| iotkit-sysinfo.h | ||
| ivshmem.h | ||
| mips_cmgcr.h | ||
| mips_cpc.h | ||
| mips_itu.h | ||
| mos6522.h | ||
| mps2-fpgaio.h | ||
| mps2-scc.h | ||
| msf2-sysreg.h | ||
| nrf51_rng.h | ||
| pca9552_regs.h | ||
| pca9552.h | ||
| pvpanic.h | ||
| stm32f2xx_syscfg.h | ||
| tmp105_regs.h | ||
| tz-mpc.h | ||
| tz-msc.h | ||
| tz-ppc.h | ||
| unimp.h | ||
| vmcoreinfo.h | ||
| zynq-xadc.h | ||