qemu-e2k/target/arm
Dongjiu Geng daf1dc5f82 target/arm: change arch timer registers access permission
Some generic arch timer registers are Config-RW in the EL0,
which means the EL0 exception level can have write permission
if it is appropriately configured.

When VM access registers, QEMU firstly checks whether they have RW
permission, then check whether it is appropriately configured.
If they are defined to read only in EL0, even though they have been
appropriately configured, they still do not have write permission.
So need to add the write permission according to ARMV8 spec when
define it.

Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Message-id: 1552395177-12608-1-git-send-email-gengdongjiu@huawei.com
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-15 11:12:29 +00:00
..
arch_dump.c
arm_ldst.h
arm-powerctl.c target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() 2019-02-28 11:03:04 +00:00
arm-powerctl.h target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() 2019-02-28 11:03:04 +00:00
arm-semi.c target/arm: Remove a handful of stray tabs 2018-08-24 13:17:48 +01:00
cpu64.c target/arm: Implement ARMv8.5-FRINT 2019-03-05 15:55:08 +00:00
cpu-qom.h arm: replace instance_post_init() 2019-01-07 16:18:42 +04:00
cpu.c target/arm: Implement ARMv8.0-PredInv 2019-03-05 15:55:07 +00:00
cpu.h target/arm: Implement ARMv8.5-FRINT 2019-03-05 15:55:08 +00:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target/arm: Split helper_msr_i_pstate into 3 2019-03-05 15:55:08 +00:00
helper-a64.h target/arm: Split helper_msr_i_pstate into 3 2019-03-05 15:55:08 +00:00
helper-sve.h target/arm: Rewrite vector gather first-fault loads 2018-10-08 14:55:03 +01:00
helper.c target/arm: change arch timer registers access permission 2019-03-15 11:12:29 +00:00
helper.h target/arm: Implement ARMv8.5-FRINT 2019-03-05 15:55:08 +00:00
idau.h qom: make interface types abstract 2018-12-11 15:45:22 -02:00
internals.h target/arm: Split helper_msr_i_pstate into 3 2019-03-05 15:55:08 +00:00
iwmmxt_helper.c
kvm32.c Revert "arm: Allow system registers for KVM guests to be changed by QEMU code" 2019-02-28 11:03:05 +00:00
kvm64.c Revert "arm: Allow system registers for KVM guests to be changed by QEMU code" 2019-02-28 11:03:05 +00:00
kvm_arm.h kvm: add kvm_arm_get_max_vm_ipa_size 2019-03-05 15:55:09 +00:00
kvm-consts.h
kvm-stub.c
kvm.c kvm: add kvm_arm_get_max_vm_ipa_size 2019-03-05 15:55:09 +00:00
machine.c Revert "arm: Allow system registers for KVM guests to be changed by QEMU code" 2019-02-28 11:03:05 +00:00
Makefile.objs target/arm: Split out vfp_helper.c 2019-02-21 18:17:45 +00:00
monitor.c qapi: make query-gic-capabilities depend on TARGET_ARM 2019-02-18 14:44:05 +01:00
neon_helper.c target/arm: Split out FPSCR.QC to a vector field 2019-02-15 09:56:41 +00:00
op_addsub.h
op_helper.c target/arm: Add set/clear_pstate_bits, share gen_ss_advance 2019-03-05 15:55:08 +00:00
pauth_helper.c target/arm: Implement pauth_computepac 2019-01-21 10:38:55 +00:00
psci.c
sve_helper.c target/arm/sve_helper: Fix compilation with clang 3.4 2018-11-28 15:31:15 +00:00
sve.decode target/arm: SVE brk[ab] merging does not have s bit 2019-01-07 15:23:45 +00:00
trace-events
translate-a64.c target/arm: Implement ARMv8.5-FRINT 2019-03-05 15:55:08 +00:00
translate-a64.h
translate-sve.c target/arm: Rely on optimization within tcg_gen_gvec_or 2019-02-15 09:56:39 +00:00
translate.c target/arm: Add set/clear_pstate_bits, share gen_ss_advance 2019-03-05 15:55:08 +00:00
translate.h target/arm: Add set/clear_pstate_bits, share gen_ss_advance 2019-03-05 15:55:08 +00:00
vec_helper.c target/arm: Add helpers for FMLAL 2019-02-28 11:03:05 +00:00
vfp_helper.c target/arm: Implement ARMv8.5-FRINT 2019-03-05 15:55:08 +00:00