qemu-e2k/target/riscv
Philippe Mathieu-Daudé 883f2c591f bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx
The 'hwaddr' type is defined in "exec/hwaddr.h" as:

    hwaddr is the type of a physical address
   (its size can be different from 'target_ulong').

All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx:

 $ fgrep define include/exec/hwaddr.h
 #define HWADDR_H
 #define HWADDR_BITS 64
 #define HWADDR_MAX UINT64_MAX
 #define TARGET_FMT_plx "%016" PRIx64
         ^^^^^^
 #define HWADDR_PRId PRId64
 #define HWADDR_PRIi PRIi64
 #define HWADDR_PRIo PRIo64
 #define HWADDR_PRIu PRIu64
 #define HWADDR_PRIx PRIx64
 #define HWADDR_PRIX PRIX64

Since hwaddr's size can be *different* from target_ulong, it is
very confusing to read one of its format using the 'TARGET_FMT_'
prefix, normally used for the target_long / target_ulong types:

$ fgrep TARGET_FMT_ include/exec/cpu-defs.h
 #define TARGET_FMT_lx "%08x"
 #define TARGET_FMT_ld "%d"
 #define TARGET_FMT_lu "%u"
 #define TARGET_FMT_lx "%016" PRIx64
 #define TARGET_FMT_ld "%" PRId64
 #define TARGET_FMT_lu "%" PRIu64

Apparently this format was missed during commit a8170e5e97
("Rename target_phys_addr_t to hwaddr"), so complete it by
doing a bulk-rename with:

 $ sed -i -e s/TARGET_FMT_plx/HWADDR_FMT_plx/g $(git grep -l TARGET_FMT_plx)

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230110212947.34557-1-philmd@linaro.org>
[thuth: Fix some warnings from checkpatch.pl along the way]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-01-18 11:14:34 +01:00
..
insn_trans RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
arch_dump.c dump: Replace opaque DumpState pointer with a typed one 2022-10-06 19:30:43 +04:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Add smstateen support 2023-01-06 10:42:55 +10:00
cpu_helper.c bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
cpu_user.h
cpu-param.h
cpu.c RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
cpu.h RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
crypto_helper.c
csr.c target/riscv: Typo fix in sstc() predicate 2023-01-06 10:42:55 +10:00
debug.c target/riscv: Add itrigger_enabled field to CPURISCVState 2023-01-06 10:42:55 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c
gdbstub.c target/riscv: Check the correct exception cause in vector GDB stub 2022-09-27 07:04:38 +10:00
helper.h target/riscv: Add itrigger support when icount is not enabled 2023-01-06 10:42:55 +10:00
insn16.decode target/riscv: fix shifts shamt value for rv128c 2022-09-07 09:18:32 +02:00
insn32.decode RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: rvv: Add mask agnostic for vv instructions 2022-09-07 09:18:32 +02:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c kvm: allow target-specific accelerator properties 2022-10-10 09:23:16 +02:00
m128_helper.c
machine.c target/riscv: Add itrigger_enabled field to CPURISCVState 2023-01-06 10:42:55 +10:00
meson.build target/riscv: Add stimecmp support 2022-09-07 09:19:15 +02:00
monitor.c bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
op_helper.c target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ 2023-01-06 10:42:55 +10:00
pmp.c target/riscv: Fix PMP propagation for tlb 2023-01-06 10:42:55 +10:00
pmp.h target/riscv: Fix PMP propagation for tlb 2023-01-06 10:42:55 +10:00
pmu.c hw/riscv: virt: Add PMU DT node to the device tree 2022-09-07 09:19:15 +02:00
pmu.h hw/riscv: virt: Add PMU DT node to the device tree 2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h
time_helper.c target/riscv: Add vstimecmp support 2022-09-07 09:19:15 +02:00
time_helper.h target/riscv: Add stimecmp support 2022-09-07 09:19:15 +02:00
trace-events
trace.h
translate.c RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
vector_helper.c cleanup: Tweak and re-run return_directly.cocci 2022-12-14 16:19:35 +01:00
XVentanaCondOps.decode