qemu-e2k/target/riscv
Bin Meng db70794ea8 target/riscv: csr: Rename HCOUNTEREN_CY and friends
The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
in fact it applies to M-mode and S-mode CSR too. Rename these macros
to have the COUNTEREN_ prefix.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210915084601.24304-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21 12:10:47 +10:00
..
insn_trans target/riscv: Use {get,dest}_gpr for RVV 2021-09-01 11:59:12 +10:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: rvb: generalized or-combine 2021-06-08 09:59:45 +10:00
cpu_bits.h target/riscv: csr: Rename HCOUNTEREN_CY and friends 2021-09-21 12:10:47 +10:00
cpu_helper.c target/riscv: Backup/restore mstatus.SD bit when virtual register swapped 2021-09-21 12:10:22 +10:00
cpu_user.h
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c target/riscv: Expose interrupt pending bits as GPIO lines 2021-09-21 07:56:49 +10:00
cpu.h target/riscv: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
csr.c target/riscv: csr: Rename HCOUNTEREN_CY and friends 2021-09-21 12:10:47 +10:00
fpu_helper.c target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
gdbstub.c target/riscv: gdbstub: Fix dynamic CSR XML generation 2021-06-24 05:00:12 -07:00
helper.h target/riscv: Reorg csr instructions 2021-09-01 11:59:12 +10:00
insn16.decode target/riscv: Consolidate RV32/64 16-bit instructions 2021-05-11 20:02:07 +10:00
insn32.decode target/riscv: Tidy trans_rvh.c.inc 2021-09-01 11:59:12 +10:00
instmap.h
internals.h target/riscv: Add basic vmstate description of CPU 2020-11-03 07:17:23 -08:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
machine.c target/riscv: Remove privilege v1.9 specific CSR related code 2021-05-11 20:01:10 +10:00
meson.build target/riscv: rvb: generalized reverse 2021-06-08 09:59:45 +10:00
monitor.c target/riscv: Remove the hardcoded SATP_MODE macro 2021-05-11 20:02:07 +10:00
op_helper.c target/riscv: Reorg csr instructions 2021-09-01 11:59:12 +10:00
pmp.c target/riscv: pmp: Fix some typos 2021-07-15 08:56:00 +10:00
pmp.h target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c accel/tcg: Add DisasContextBase argument to translator_ld* 2021-09-14 12:00:20 -07:00
vector_helper.c target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00