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Artyom Tarasenko 3390537b5d
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs 
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.

"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"

Integer stores of all sizes are allowed with these ASIs.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
 		2017-01-18 22:03:44 +01:00
..
alpha cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
arm This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
cris qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
i386 This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
lm32 qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
m68k This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
microblaze cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
mips cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
moxie qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
openrisc cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
ppc This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
s390x This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
sh4 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
sparc target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs 2017-01-18 22:03:44 +01:00
tilegx qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
tricore qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
unicore32 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
xtensa cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00