qemu-e2k/target/sparc
Artyom Tarasenko 3390537b5d
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.

"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"

Integer stores of all sizes are allowed with these ASIs.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
..
Makefile.objs
TODO
asi.h target-sparc: implement UA2005 scratchpad registers 2017-01-18 22:03:44 +01:00
cc_helper.c
cpu-qom.h
cpu.c target-sparc: implement UA2005 GL register 2017-01-18 22:03:44 +01:00
cpu.h target-sparc: store the UA2005 entries in sun4u format 2017-01-18 22:03:44 +01:00
fop_helper.c
gdbstub.c
helper.c
helper.h target-sparc: implement UA2005 GL register 2017-01-18 22:03:44 +01:00
int32_helper.c
int64_helper.c target-sparc: implement UA2005 GL register 2017-01-18 22:03:44 +01:00
ldst_helper.c target-sparc: store the UA2005 entries in sun4u format 2017-01-18 22:03:44 +01:00
machine.c target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs 2017-01-18 22:03:44 +01:00
mmu_helper.c target-sparc: add more registers to dump_mmu 2017-01-18 22:03:44 +01:00
monitor.c
trace-events
translate.c target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs 2017-01-18 22:03:44 +01:00
vis_helper.c
win_helper.c target-sparc: implement UA2005 GL register 2017-01-18 22:03:44 +01:00