Peter Maydell ed336850e8 target-arm: Fix TCG temp handling in 64 bit cp writes ... Fix errors in the TCG temp handling in the 64 bit coprocessor write path: we were reusing a 32 bit temp after it had been freed by store_reg(), and failing to free a 64 bit temp. This bug has no visible effect at this point because there aren't any non-NOP 64 bit registers yet; it needs to be fixed as a prerequisite for the 64 bit registers in LPAE support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2012-07-12 10:59:53 +00:00
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arm-semi.c
cpu-qom.h	target-arm: Convert cp15 crn=1 registers	2012-06-20 12:08:22 +00:00
cpu.c	target-arm: Remove ARM_CPUID_* macros	2012-06-20 12:13:28 +00:00
cpu.h	target-arm: Remove ARM_CPUID_* macros	2012-06-20 12:13:28 +00:00
helper.c	target-arm: Fix some copy-and-paste errors in cp register names	2012-07-12 10:58:36 +00:00
helper.h	target-arm: Remove remaining old cp15 infrastructure	2012-06-20 12:13:04 +00:00
iwmmxt_helper.c
machine.c	target-arm: Remove c0_cachetype CPUARMState field	2012-06-20 12:11:49 +00:00
Makefile.objs	build: move other target-*/ objects to nested Makefile.objs	2012-06-07 09:21:11 +02:00
neon_helper.c
op_addsub.h
op_helper.c	target-arm: initial coprocessor register framework	2012-06-20 12:01:02 +00:00
translate.c	target-arm: Fix TCG temp handling in 64 bit cp writes	2012-07-12 10:59:53 +00:00