OpenE2K/qemu-e2k
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qemu-e2k/target/ppc
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Víctor Colombo bf3dd1e6d0 target/ppc: Change MSR_* to follow POWER ISA numbering convention 
Today we have the issue where MSR_* values are the 'inverted order'
bit numbers from what the ISA specifies. e.g. MSR_LE is bit 63 but
is defined as 0 in QEMU.

Add a macro to be used to convert from QEMU order to ISA order.

This solution requires less changes than to use the already defined
PPC_BIT macro, which would turn MSR_* in masks instead of the numbers
itself.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-23-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-05 15:36:17 -03:00
..
translate target/ppc: implement xscvqp[su]qz 2022-04-20 18:00:30 -03:00
arch_dump.c Replace config-time define HOST_WORDS_BIGENDIAN 2022-04-06 10:50:37 +02:00
compat.c
cpu_init.c target/ppc: Remove msr_hv macro 2022-05-05 15:36:17 -03:00
cpu-models.c target/ppc: Remove PowerPC 601 CPUs 2022-02-09 09:08:55 +01:00
cpu-models.h target/ppc: Remove PowerPC 601 CPUs 2022-02-09 09:08:55 +01:00
cpu-param.h
cpu-qom.h target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro 2022-03-06 22:23:09 +01:00
cpu.c target/ppc: Remove fpscr_* macros from cpu.h 2022-05-05 15:36:17 -03:00
cpu.h target/ppc: Change MSR_* to follow POWER ISA numbering convention 2022-05-05 15:36:17 -03:00
dfp_helper.c target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree 2021-11-09 10:32:52 +11:00
excp_helper.c target/ppc: Remove msr_hv macro 2022-05-05 15:36:17 -03:00
fpu_helper.c target/ppc: Remove fpscr_* macros from cpu.h 2022-05-05 15:36:17 -03:00
gdbstub.c target/ppc: Remove msr_le macro 2022-05-05 15:36:17 -03:00
helper_regs.c target/ppc: Remove msr_de macro 2022-05-05 15:36:17 -03:00
helper_regs.h
helper.h target/ppc: implement xscvqp[su]qz 2022-04-20 18:00:30 -03:00
insn32.decode target/ppc: implement xscvqp[su]qz 2022-04-20 18:00:30 -03:00
insn64.decode target/ppc: implement plxssp/pstxssp 2022-03-02 06:51:38 +01:00
int_helper.c Replace config-time define HOST_WORDS_BIGENDIAN 2022-04-06 10:50:37 +02:00
internal.h compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
Kconfig
kvm_ppc.h
kvm-stub.c
kvm.c target/ppc: Remove msr_ts macro 2022-05-05 15:36:17 -03:00
machine.c target/ppc: Remove msr_ts macro 2022-05-05 15:36:17 -03:00
mem_helper.c target/ppc: Remove msr_hv macro 2022-05-05 15:36:17 -03:00
meson.build target/ppc: make power8-pmu.c CONFIG_TCG only 2022-03-02 06:51:36 +01:00
misc_helper.c target/ppc: Remove msr_hv macro 2022-05-05 15:36:17 -03:00
mmu_common.c target/ppc: Remove msr_dr macro 2022-05-05 15:36:17 -03:00
mmu_helper.c target/ppc: Remove msr_cm macro 2022-05-05 15:36:17 -03:00
mmu-book3s-v3.c
mmu-book3s-v3.h
mmu-books.h
mmu-hash32.c target/ppc: Remove PowerPC 601 CPUs 2022-02-09 09:08:55 +01:00
mmu-hash32.h target/ppc: Remove PowerPC 601 CPUs 2022-02-09 09:08:55 +01:00
mmu-hash64.c target/ppc: fix Hash64 MMU update of PTE bit R 2021-11-29 21:00:08 +01:00
mmu-hash64.h target/ppc: fix Hash64 MMU update of PTE bit R 2021-11-29 21:00:08 +01:00
mmu-radix64.c target/ppc: Remove msr_hv macro 2022-05-05 15:36:17 -03:00
mmu-radix64.h target/ppc: Check effective address validity 2022-01-04 07:55:34 +01:00
monitor.c
power8-pmu-regs.c.inc target/ppc: enable PMU instruction count 2021-12-17 17:57:18 +01:00
power8-pmu.c target/ppc: trigger PERFM EBBs from power8-pmu.c 2022-03-02 06:51:36 +01:00
power8-pmu.h target/ppc: make power8-pmu.c CONFIG_TCG only 2022-03-02 06:51:36 +01:00
spr_common.h target/ppc: Move common SPR functions out of cpu_init 2022-02-18 08:34:15 +01:00
tcg-stub.c
timebase_helper.c target/ppc: Remove PowerPC 601 CPUs 2022-02-09 09:08:55 +01:00
trace-events target/ppc: Improve KVM hypercall trace 2022-04-20 18:00:30 -03:00
trace.h
translate.c exec/translator: Pass the locked filepointer to disas_log hook 2022-04-20 10:51:11 -07:00
user_only_helper.c