qemu-e2k/target/riscv
Daniel Henrique Barboza efa365b711 target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
riscv_cpu_add_misa_properties() is being used to fill the missing KVM
MISA properties but it is a TCG helper that was adapted to do so. We'll
move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
the remaining MISA properties on its own.

Do not use riscv_cpu_add_misa_properties(). Let's create a new array
with all available MISA bits we support that can be read by KVM. The
array is zero terminate to allow us to iterate through it without
knowing its size.

Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM
MISA properties as usual and then use this array to add any missing MISA
properties with the riscv_cpu_add_kvm_unavail_prop() helper.

Note that we're creating misa_bits[], and not using the existing
'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa
related functions and it doesn't have all MISA bits we support. Commit
0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the
full context.

While we're at it, move both satp and the multi-letter extension
properties to kvm_riscv_add_cpu_user_properties() as well.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-10-12 12:21:37 +10:00
..
insn_trans tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
kvm target/riscv/kvm: do not use riscv_cpu_add_misa_properties() 2023-10-12 12:21:37 +10:00
tcg target/riscv: move riscv_tcg_ops to tcg-cpu.c 2023-10-12 11:59:03 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Update CSR bits name for svadu extension 2023-09-11 11:45:55 +10:00
cpu_cfg.h target/riscv: Add Zihintntl extension ISA string to DTS 2023-09-11 11:45:55 +10:00
cpu_helper.c target/riscv: Update CSR bits name for svadu extension 2023-09-11 11:45:55 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h target/riscv: add 'max' CPU type 2023-10-12 11:39:33 +10:00
cpu.c target/riscv/kvm: do not use riscv_cpu_add_misa_properties() 2023-10-12 12:21:37 +10:00
cpu.h target/riscv/kvm: do not use riscv_cpu_add_misa_properties() 2023-10-12 12:21:37 +10:00
crypto_helper.c target/riscv: Use accelerated helper for AES64KS1I 2023-09-11 11:45:55 +10:00
csr.c target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c 2023-10-12 11:57:46 +10:00
debug.c target/riscv: Allocate itrigger timers only once 2023-09-11 11:45:55 +10:00
debug.h target/riscv: Allocate itrigger timers only once 2023-09-11 11:45:55 +10:00
fpu_helper.c
gdbstub.c
helper.h target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
insn16.decode
insn32.decode target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
instmap.h
internals.h
Kconfig
m128_helper.c
machine.c
meson.build target/riscv: move KVM only files to kvm subdir 2023-10-12 12:20:24 +10:00
monitor.c
op_helper.c
pmp.c target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes 2023-09-11 11:45:55 +10:00
pmp.h
pmu.c
pmu.h
riscv-qmp-cmds.c
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c accel/tcg: Replace CPUState.env_ptr with cpu_env() 2023-10-04 11:03:54 -07:00
vcrypto_helper.c target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
vector_helper.c tcg: Correct invalid mentions of 'softmmu' by 'system-mode' 2023-10-07 19:02:33 +02:00
vector_internals.c target/riscv: Refactor some of the generic vector functionality 2023-09-11 11:45:54 +10:00
vector_internals.h target/riscv: Refactor some of the generic vector functionality 2023-09-11 11:45:55 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c