Peter Maydell f00f57f344 This PR includes multiple fixes and features for RISC-V: ... - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAl9aa4YACgkQIeENKd+X cFTJjgf5ASfFIO5HqP1l80/UM5Pswyq0IROZDq0ItZa6U4EPzLXoE2N0POriIj4h Ds2JbMg0ORDqY0VbSxHlgYHMgJ9S6cuVOMnATsPG0d2jaJ3gSxLBu5k/1ENqe+Vw sSYXZv5uEAUfOFz99zbuhKHct5HzlmBFW9dVHdflUQS+cRgsSXq27mz1BvZ8xMWl lMhwubqdoNx0rOD3vKnlwrxaf54DcJ2IQT3BtTCjEar3tukdNaLijAuwt2hrFyr+ IwpeFXA/NWar+mXP3M+BvcLaI33j73/ac2+S5SJuzHGp/ot5nT5gAuq3PDEjHMeS t6z9Exp776VXxNE2iUA5NB65Yp3/6w== =07oA -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv # gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/riscv/trace-events		2020-09-13 20:29:35 +01:00
..
aspeed_gpio.c	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
bcm2835_gpio.c
gpio_key.c	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
imx_gpio.c
Kconfig	hw/riscv: Move sifive_gpio model to hw/gpio	2020-09-09 15:54:19 -07:00
max7310.c	trivial patches pull request 20200911	2020-09-12 14:23:15 +01:00
meson.build	hw/riscv: Move sifive_gpio model to hw/gpio	2020-09-09 15:54:19 -07:00
mpc8xxx.c	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
nrf51_gpio.c
omap_gpio.c	hw/gpio/omap_gpio: Replace fprintf() by qemu_log_mask(GUEST_ERROR)	2020-09-09 15:27:48 +02:00
pl061.c	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
puv3_gpio.c	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
sifive_gpio.c	hw/riscv: Move sifive_gpio model to hw/gpio	2020-09-09 15:54:19 -07:00
trace-events	hw/riscv: Move sifive_gpio model to hw/gpio	2020-09-09 15:54:19 -07:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
zaurus.c	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00