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qemu-e2k/target/riscv
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Philippe Mathieu-Daudé f4063f9c31 meson: Introduce target-specific Kconfig 
Add a target-specific Kconfig. We need the definitions in Kconfig so
the minikconf tool can verify they exits. However CONFIG_FOO is only
enabled for target foo via the meson.build rules.

Two architecture have a particularity, ARM and MIPS. As their
translators have been split you can potentially build a plain 32 bit
build along with a 64-bit version including the 32-bit subset.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210131111316.232778-6-f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210707131744.26027-2-alex.bennee@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 		2021-07-09 18:21:34 +02:00
..
insn_trans target/riscv: rvb: add/shift with prefix zero-extend 2021-06-08 09:59:45 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: rvb: generalized or-combine 2021-06-08 09:59:45 +10:00
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c target/riscv: rvb: add b-ext version cpu option 2021-06-08 09:59:46 +10:00
cpu.h target/riscv: rvb: add b-ext version cpu option 2021-06-08 09:59:46 +10:00
cpu_bits.h target/riscv: fix wfi exception behavior 2021-06-08 09:59:42 +10:00
cpu_helper.c target/riscv: Remove the hardcoded SATP_MODE macro 2021-05-11 20:02:07 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
csr.c target/riscv: Remove the hardcoded SATP_MODE macro 2021-05-11 20:02:07 +10:00
fpu_helper.c target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
gdbstub.c target/riscv: gdbstub: Fix dynamic CSR XML generation 2021-06-24 05:00:12 -07:00
helper.h target/riscv: rvb: generalized or-combine 2021-06-08 09:59:45 +10:00
insn16.decode target/riscv: Consolidate RV32/64 16-bit instructions 2021-05-11 20:02:07 +10:00
insn32.decode target/riscv: rvb: add/shift with prefix zero-extend 2021-06-08 09:59:45 +10:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: Add basic vmstate description of CPU 2020-11-03 07:17:23 -08:00
machine.c target/riscv: Remove privilege v1.9 specific CSR related code 2021-05-11 20:01:10 +10:00
meson.build target/riscv: rvb: generalized reverse 2021-06-08 09:59:45 +10:00
monitor.c target/riscv: Remove the hardcoded SATP_MODE macro 2021-05-11 20:02:07 +10:00
op_helper.c target/riscv: fix wfi exception behavior 2021-06-08 09:59:42 +10:00
pmp.c target/riscv/pmp: Add assert for ePMP operations 2021-06-08 09:59:43 +10:00
pmp.h target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: Use target_ulong for the DisasContext misa 2021-06-24 05:00:12 -07:00
vector_helper.c target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00