qemu-e2k/linux-user
Emilio G. Cota 3468b59e18 tcg: enable multiple TCG contexts in softmmu
This enables parallel TCG code generation. However, we do not take
advantage of it yet since tb_lock is still held during tb_gen_code.

In user-mode we use a single TCG context; see the documentation
added to tcg_region_init for the rationale.

Note that targets do not need any conversion: targets initialize a
TCGContext (e.g. defining TCG globals), and after this initialization
has finished, the context is cloned by the vCPU threads, each of
them keeping a separate copy.

TCG threads claim one entry in tcg_ctxs[] by atomically increasing
n_tcg_ctxs. Do not be too annoyed by the subsequent atomic_read's
of that variable and tcg_ctxs; they are there just to play nice with
analysis tools such as thread sanitizer.

Note that we do not allocate an array of contexts (we allocate
an array of pointers instead) because when tcg_context_init
is called, we do not know yet how many contexts we'll use since
the bool behind qemu_tcg_mttcg_enabled() isn't set yet.

Previous patches folded some TCG globals into TCGContext. The non-const
globals remaining are only set at init time, i.e. before the TCG
threads are spawned. Here is a list of these set-at-init-time globals
under tcg/:

Only written by tcg_context_init:
- indirect_reg_alloc_order
- tcg_op_defs
Only written by tcg_target_init (called from tcg_context_init):
- tcg_target_available_regs
- tcg_target_call_clobber_regs
- arm: arm_arch, use_idiv_instructions
- i386: have_cmov, have_bmi1, have_bmi2, have_lzcnt,
        have_movbe, have_popcnt
- mips: use_movnz_instructions, use_mips32_instructions,
        use_mips32r2_instructions, got_sigill (tcg_target_detect_isa)
- ppc: have_isa_2_06, have_isa_3_00, tb_ret_addr
- s390: tb_ret_addr, s390_facilities
- sparc: qemu_ld_trampoline, qemu_st_trampoline (build_trampolines),
         use_vis3_instructions

Only written by tcg_prologue_init:
- 'struct jit_code_entry one_entry'
- aarch64: tb_ret_addr
- arm: tb_ret_addr
- i386: tb_ret_addr, guest_base_flags
- ia64: tb_ret_addr
- mips: tb_ret_addr, bswap32_addr, bswap32u_addr, bswap64_addr

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24 13:53:42 -07:00
..
aarch64
alpha
arm linux-user: Tidy and enforce reserved_va initialization 2017-10-16 16:00:56 +03:00
cris
host Replace 'struct ucontext' with 'ucontext_t' type 2017-07-20 10:10:28 +01:00
hppa
i386
m68k
microblaze
mips
mips64
nios2
openrisc
ppc
s390x
sh4
sparc sparc: embed sparc_def_t into CPUSPARCState 2017-09-01 11:54:24 -03:00
sparc64
tilegx
unicore32
x86_64
elfload.c linux-user: Allow -R values up to 0xffff0000 for 32-bit ARM guests 2017-10-16 16:00:56 +03:00
errno_defs.h
flat.h
flatload.c
ioctls.h linux-user: Add some random ioctls 2017-10-16 21:00:04 +03:00
linux_loop.h
linuxload.c
m68k-sim.c
main.c tcg: introduce regions to split code_gen_buffer 2017-10-24 13:53:42 -07:00
Makefile.objs
mmap.c
qemu.h
safe-syscall.S
signal.c target/m68k,linux-user: manage FP registers in ucontext 2017-10-16 16:00:56 +03:00
socket.h
strace.c linux-user: fix O_TMPFILE handling 2017-10-16 16:00:56 +03:00
strace.list
syscall_defs.h Linux-user updates for Qemu 2.11 2017-10-19 14:39:30 +01:00
syscall_types.h
syscall.c tcg: enable multiple TCG contexts in softmmu 2017-10-24 13:53:42 -07:00
target_flat.h
trace-events trace-events: fix code style: print 0x before hex numbers 2017-08-01 12:13:07 +01:00
uaccess.c
uname.c
uname.h
vm86.c