Christoph Müllner f6f72338d8 disas/riscv: Add support for XVentanaCondOps ... This patch adds XVentanaCondOps support to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-07-10 22:29:14 +10:00
..
alpha.c
capstone.c	disas: use result of ->read_memory_func	2022-10-06 11:53:40 +01:00
cris.c
disas-internal.h	disas: Move softmmu specific code to separate file	2023-05-11 09:49:55 +01:00
disas-mon.c	disas: Move softmmu specific code to separate file	2023-05-11 09:49:55 +01:00
disas.c	disas: Move disas.c into the target-independent source set	2023-05-11 09:51:07 +01:00
hexagon.c
hppa.c
m68k.c
meson.build	disas/riscv: Add support for XVentanaCondOps	2023-07-10 22:29:14 +10:00
microblaze.c
mips.c	disas/mips: Fix branch displacement for BEQZC and BNEZC	2022-10-31 11:32:07 +01:00
nanomips.c	disas/nanomips: Tidy read for 48-bit opcodes	2022-11-08 01:04:25 +01:00
nios2.c
riscv-xventana.c	disas/riscv: Add support for XVentanaCondOps	2023-07-10 22:29:14 +10:00
riscv-xventana.h	disas/riscv: Add support for XVentanaCondOps	2023-07-10 22:29:14 +10:00
riscv.c	disas/riscv: Add support for XVentanaCondOps	2023-07-10 22:29:14 +10:00
riscv.h	disas/riscv: Encapsulate opcode_data into decode	2023-07-10 22:29:14 +10:00
sh4.c
sparc.c
xtensa.c