qemu-e2k/target
Peter Maydell f94a6df5dd target/arm: Correctly implement Feat_DoubleLock
The architecture defines the OS DoubleLock as a register which
(similarly to the OS Lock) suppresses debug events for use in CPU
powerdown sequences.  This functionality is required in Arm v7 and
v8.0; from v8.2 it becomes optional and in v9 it must not be
implemented.

Currently in QEMU we implement the OSDLR_EL1 register as a NOP.  This
is wrong both for the "feature implemented" and the "feature not
implemented" cases: if the feature is implemented then the DLK bit
should read as written and cause suppression of debug exceptions, and
if it is not implemented then the bit must be RAZ/WI.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-07 11:38:36 +01:00
..
alpha
arm target/arm: Correctly implement Feat_DoubleLock 2022-07-07 11:38:36 +01:00
avr target/avr: Drop avr_cpu_memory_rw_debug() 2022-06-20 13:11:36 -07:00
cris
hexagon
hppa
i386 Fix 'writeable' typos 2022-06-08 19:38:47 +01:00
loongarch target/loongarch: Clean up tlb when cpu reset 2022-07-05 16:17:53 +05:30
m68k target/m68k: Make semihosting system only 2022-06-28 10:13:22 +05:30
microblaze
mips target/mips: Drop pread and pwrite syscalls from semihosting 2022-06-28 10:15:12 +05:30
nios2 target/nios2: Move nios2-semi.c to nios2_softmmu_ss 2022-06-28 10:18:57 +05:30
openrisc
ppc target/ppc: Fix MPC8555 and MPC8560 core type to e500v1 2022-07-06 10:30:01 -03:00
riscv target/riscv: Update default priority table for local interrupts 2022-07-03 10:03:20 +10:00
rx
s390x Fix 'writeable' typos 2022-06-08 19:38:47 +01:00
sh4
sparc
tricore
xtensa
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00