qemu-e2k/target
Tobias Röhmel faa1451e7b target/arm: Make stage_2_format for cache attributes optional
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2 descriptor) and then converting back to do the attribute
combination, allow combined_attrs_nofwb() to accept s2 attributes
that are already in the MAIR format.

We move the assert() to combined_attrs_fwb(), because that function
really does require a VMSA stage 2 attribute format. (We will never
get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05 11:51:09 +00:00
..
alpha accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
arm target/arm: Make stage_2_format for cache attributes optional 2023-01-05 11:51:09 +00:00
avr target/avr: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
cris target/cris: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
hexagon 1) 2022-12-18 17:02:11 +00:00
hppa target/hppa: Fix fid instruction emulation 2022-12-19 23:14:06 +01:00
i386 target/i386: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
loongarch target/loongarch: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
m68k target/m68k: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
microblaze target/microblaze: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
mips target/mips: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
nios2 target/nios2: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
openrisc target/openrisc: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
ppc target/ppc: Check DEXCR on hash{st, chk} instructions 2022-12-21 14:17:55 -03:00
riscv target/riscv: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
rx target/rx: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
s390x target/s390x: The MVCP and MVCS instructions are not privileged 2022-12-15 15:02:34 +01:00
sh4 target/sh4: Mask restore of env->flags from tb->flags 2022-12-18 09:36:07 -08:00
sparc target/sparc: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
tricore target/tricore: Fix gdbstub write to address registers 2022-12-18 09:39:17 -08:00
xtensa target/xtensa: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00