Mayuresh Chitale fb3f3730e4 target/riscv: generate virtual instruction exception ... This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221016124726.102129-4-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-06 10:42:55 +10:00
..
insn_trans	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
arch_dump.c	dump: Replace opaque DumpState pointer with a typed one	2022-10-06 19:30:43 +04:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Add smstateen support	2023-01-06 10:42:55 +10:00
cpu_helper.c	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Convert to 3-phase reset	2022-12-16 15:58:15 +00:00
cpu.h	target/riscv: Add smstateen support	2023-01-06 10:42:55 +10:00
crypto_helper.c
csr.c	target/riscv: smstateen check for h/s/envcfg	2023-01-06 10:42:55 +10:00
debug.c	cleanup: Tweak and re-run return_directly.cocci	2022-12-14 16:19:35 +01:00
debug.h	target/riscv: debug: Add initial support of type 6 trigger	2022-09-27 11:23:57 +10:00
fpu_helper.c
gdbstub.c
helper.h	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
insn16.decode
insn32.decode	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c	kvm: allow target-specific accelerator properties	2022-10-10 09:23:16 +02:00
m128_helper.c
machine.c	target/riscv: Add smstateen support	2023-01-06 10:42:55 +10:00
meson.build
monitor.c
op_helper.c
pmp.c	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
pmp.h	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
pmu.c
pmu.h
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: generate virtual instruction exception	2023-01-06 10:42:55 +10:00
vector_helper.c	cleanup: Tweak and re-run return_directly.cocci	2022-12-14 16:19:35 +01:00
XVentanaCondOps.decode