5de56742a3
These instructions do not trap when SVE is disabled in EL0, causing them to be executed with wrong size information. Signed-off-by: Amir Charif <amir.charif@cea.fr> Message-id: 1552579248-31025-1-git-send-email-amir.charif@cea.fr Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added 'target/arm' prefix to subject] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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alpha | ||
arm | ||
cris | ||
hppa | ||
i386 | ||
lm32 | ||
m68k | ||
microblaze | ||
mips | ||
moxie | ||
nios2 | ||
openrisc | ||
ppc | ||
riscv | ||
s390x | ||
sh4 | ||
sparc | ||
tilegx | ||
tricore | ||
unicore32 | ||
xtensa |