Max Filippov ff35a7d1a1 target/xtensa: move FSR/FCR register accessors ... Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as they are FPU2000-specific. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2020-08-21 12:48:15 -07:00
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alpha	meson: target	2020-08-21 06:30:35 -04:00
arm	meson: target	2020-08-21 06:30:35 -04:00
avr	meson: target	2020-08-21 06:30:35 -04:00
cris	meson: target	2020-08-21 06:30:35 -04:00
hppa	meson: target	2020-08-21 06:30:35 -04:00
i386	meson: target	2020-08-21 06:30:35 -04:00
lm32	meson: target	2020-08-21 06:30:35 -04:00
m68k	meson: target	2020-08-21 06:30:35 -04:00
microblaze	meson: target	2020-08-21 06:30:35 -04:00
mips	meson: target	2020-08-21 06:30:35 -04:00
moxie	meson: target	2020-08-21 06:30:35 -04:00
nios2	meson: target	2020-08-21 06:30:35 -04:00
openrisc	meson: target	2020-08-21 06:30:35 -04:00
ppc	meson: target	2020-08-21 06:30:35 -04:00
riscv	meson: target	2020-08-21 06:30:35 -04:00
rx	meson: target	2020-08-21 06:30:35 -04:00
s390x	meson: link emulators without Makefile.target	2020-08-21 06:30:40 -04:00
sh4	meson: target	2020-08-21 06:30:35 -04:00
sparc	meson: target	2020-08-21 06:30:35 -04:00
tilegx	meson: target	2020-08-21 06:30:35 -04:00
tricore	meson: target	2020-08-21 06:30:35 -04:00
unicore32	meson: target	2020-08-21 06:30:35 -04:00
xtensa	target/xtensa: move FSR/FCR register accessors	2020-08-21 12:48:15 -07:00
meson.build	meson: target	2020-08-21 06:30:35 -04:00