Paolo Bonzini abff1abfe8 meson: target ... Similar to hw_arch, each architecture defines two sourceset which are placed in dictionaries target_arch and target_softmmu_arch. These are then picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2020-08-21 06:30:35 -04:00
..
insn_trans	meson: rename included C source files to .c.inc	2020-08-21 06:18:30 -04:00
cpu_bits.h	target/riscv: support vector extension csr	2020-07-02 09:19:32 -07:00
cpu_helper.c	target/riscv: Report errors validating 2nd-stage PTEs	2020-06-19 08:24:07 -07:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: configure and turn on vector extension from command line	2020-07-02 09:19:34 -07:00
cpu.h	target/riscv: fix vill bit index in vtype register	2020-07-13 17:25:37 -07:00
csr.c	target/riscv: Fix the range of pmpcfg of CSR funcion table	2020-07-22 09:41:36 -07:00
fpu_helper.c	target/riscv: vector floating-point classify instructions	2020-07-02 09:19:33 -07:00
gdbstub.c
helper.h	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode	target/riscv: add vector amo operations	2020-07-02 09:19:33 -07:00
insn32.decode	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00
instmap.h
internals.h	target/riscv: integer scalar move instruction	2020-07-02 09:19:33 -07:00
meson.build	meson: target	2020-08-21 06:30:35 -04:00
monitor.c	target/riscv: Drop support for ISA spec version 1.09.1	2020-06-03 09:11:51 -07:00
op_helper.c	target/riscv: Implement checks for hfence	2020-06-19 08:24:07 -07:00
pmp.c	target/riscv: Fix pmp NA4 implementation	2020-07-13 17:25:37 -07:00
pmp.h
trace-events
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	meson: target	2020-08-21 06:30:35 -04:00
vector_helper.c	target/riscv/vector_helper: Fix build on 32-bit big endian hosts	2020-08-05 10:43:45 +02:00