Fix mem op= mem bug in trans.ml (via not terribly good fix). Closes #111.

This commit is contained in:
Graydon Hoare 2010-07-22 12:11:39 -07:00
parent 2c24f70cf4
commit c96634af4b
3 changed files with 27 additions and 1 deletions

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@ -429,6 +429,7 @@ TEST_XFAILS_LLVM := $(addprefix test/run-pass/, \
generic-tag.rs \
import.rs \
inner-module.rs \
iter-range.rs \
large-records.rs \
lazy-and-or.rs \
lazy-init.rs \

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@ -4343,8 +4343,15 @@ let trans_visitor
trans_vec_append dst_cell dst_ty src_oper (atom_type cx a_src)
| _ ->
let (dst_cell, _) = deref_ty DEREF_none false dst_cell dst_ty in
let bits = Il.operand_bits word_bits src_oper in
(*
* FIXME: X86-ism going via a vreg; mem op= mem doesn't work and
* IL lacks sufficient brains to cope just now.
*)
let src = Il.Reg (Il.next_vreg (emitter()), Il.ValTy bits) in
let op = trans_binop binop in
emit (Il.binary op dst_cell (Il.Cell dst_cell) src_oper);
mov src src_oper;
emit (Il.binary op dst_cell (Il.Cell dst_cell) (Il.Cell src));
and trans_call id dst flv args =

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@ -0,0 +1,18 @@
iter range(int a, int b) -> int {
check (a < b);
let int i = a;
while (i < b) {
put i;
i += 1;
}
}
fn main() {
let int sum = 0;
for each (int x in range(0, 100)) {
sum += x;
}
log sum;
}